Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
1999-10-26
2002-05-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S406000, C438S407000, C438S455000, C438S766000
Reexamination Certificate
active
06391658
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods for forming arrays of microelectronic elements, such as magnetoresistive memory elements and FET's (field effect transistors).
An embodiment of the present invention relates to a nonvolatile memory storage array for computers and portable electronics, fabricated on a Si wafer substrate with integrated Si electronics, and using a magnetoresistive structures in each memory cell. Specifically in relation to magnetoresistive memory elements, an embodiment of this invention concerns a new structure for a memory cell consisting of a magnetic tunnel junction and a diode, similar to the cell described in U.S. Pat. No. 5,640,343 by Gallagher, et al. This invention also includes a fabrication method for said new structure.
According to an embodiment of the present invention, the new structure described herein comprises a single crystal Si diode located atop a conducting “via” (a metallic or other conducting channel through a lower conductivity layer of Si or the like) of small crossectional area, and further comprises a magnetic tunnel junction (MTJ) located atop said diode. The novel fabrication method uses a wafer bonding process to place such a single crystal Si (SCS) diode atop the conducting via.
DESCRIPTION OF THE PRIOR ART
Previously, magnetic memory cells consisting of a magnetic tunnel junction and a diode (herein called “MagRAM”) have been described in U.S. Pat. No. 5,640,343 by Gallagher, et al (IBM) and also in U.S. Pat. No. 5,734,605 by Zhu, et al (Motorola). Arrays of said memory cells were described in both of these patents. Generally, each MagRAM memory cell contains two magnetic regions separated by a thin dielectric layer through which electron tunnelling occurs and the dielectric is known as the tunnel barrier. A first magnetic layer has a fixed magnetization axis and serves as a magnetic reference layer and is composed of relatively permanent (“hard”) magnetic materials. The tunnel barrier is sandwiched between the first and second magnetic layers. The second magnetic layer is relatively easily switched between 2 magnetic states, which are aligned parallel and anti-parallel to the magnetic axis of the first reference layer. The first and second magnetic layers and the tunnel barrier comprise a trilayer MTJ, and the electrical resistance of said MTJ has two well defined values corresponding to the two alignment states of the second (“free”) magnetic layer. Information storage is performed by assigning 0 and 1 to the two electrical resistance states of each cell.
Arrays of MTJ memory cells containing upwards of 1,000 cells are very useful. An extremely high information storage density suitable for very large scale integrated (VLSI) circuits is possible using a very compact (small area) MTJ cell design that is vertically integrated, and wherein each cell consists of an MTJ and a diode in a vertical stack located at the intersection of two metal thin film wires, and the MTJ plus diode stack electrically contacts each of said thin film wires. This vertically integrated memory cell occupies a minimum area of the VLSI chip yielding the maximum information density, and is known as the “crosspoint architecture”.
In such a crosspoint architecture memory cell, a diode is located atop the bottom metal conductor (row line). An MTJ is located atop the diode, electrically in series with the diode. The top metal conductor is above and in contact with the MTJ. When the resistance of the cell is sensed, the sense current flows through only one memory cell, instead of through N cells as in conventional series architecture magnetoresistive memories. The signal-to-noise ratio (SNR) of the crosspoint array containing N elements is N times larger than the conventional array containing N elements. Alternatively, the SNR can be the same and the sense power of the crosspoint architecture can be reduced by a factor of N×N (or N squared).
The sensing operation is a measurement of resistance, and any series resistance that is similar in magnitude to the MTJ resistance detracts from the signal. Thus, the diode should have a small series resistance, and this diode resistance should be uniform throughout an array of many diodes (memory cells). The diode atop the row line may be formed in a small lithographically defined piece of semiconductor such as Si, and furthermore this Si piece (“island”) may consist of 1 large crystal grain (single crystal or monocrystalline), or may consist of multiple smaller crystal grains (polycrystalline). The polycrystalline state is typical of thin film semiconductors.
The advantages of using a single crystal Si (SCS) diode (as opposed to a thin film diode) in the MagRAM cell, and in high density arrays of these cells, are improved electrical performance, and more uniform electrical characteristics in large arrays of diodes (e.g. 1,000×1,000 arrays). Specifically, the electrical performance of an SCS diode includes a lower series resistance (higher forward current density) and a higher rectification (ratio of Forward/Reverse bias currents). With a lower diode resistance, a given value of the sense current during the Read operation requires a lower voltage, and hence the power consumption is lower. Also, a higher diode conductivity interferes less with the Read operation, when the conductivity of the MTJ device used to store the data is sensed. With a higher diode rectification, less current is passed in the reverse bias direction, and so overall power consumption of the array is reduced.
SUMMARY OF THE INVENTION
The present invention broadly provides a method of forming an array of microelectronic elements, said method comprising the steps of:
a) preparing a first wafer of semiconductor material by implanting, through a first surface of said first wafer, ions to a planar region at a selected depth therein, said ions being ions of an element selected from hydrogen and the noble gases,
b) preparing a second wafer of semiconductor material, said second wafer comprising a layer of dielectric material having a second surface, a pattern of mutually electrically isolated metal conductors being disposed within said layer, said metal conductors comprising spaced apart conducting regions extending to and being exposed at said second surface,
c) placing said first wafer over said second wafer with said first surface of said first wafer in juxtaposed adherence and electrical contact with said second surface and with said conducting regions exposed thereat, and
d) inducing a fracture along said planar region of said first wafer to leave a semiconductor layer of said first wafer bounded between said first surface and a fracture surface formed in said planar region, said first surface remaining in electrically contacting adherence with said second surface.
Preferably, step a) comprises a further step of forming a semiconductor device in the aforesaid semiconductor layer above each of said conducting regions of said metal conductors.
According to a preferred embodiment, the aforesaid microelectronic elements are magnetoresistive memory elements and the method comprising the further step of forming an MTJ structure in electrical contact with said semiconductor layer above each of said conducting regions of said metal conductors. The semiconductor device can be a diode which is in electrical contact with the magnetoresistive memory element.
According to another preferred embodiment, step a) comprises a further step of forming a field effect transistor at positions in said semiconductor layer which overlie said conducting regions of said metal conductors, each of said conducting regions (e.g. metal-filled via) serving as a first gate electrode of said field effect transistor. Moreover, step a) may then comprise a further step of forming a first oxide layer on said first surface of said first wafer before step c). Advantageously, a second oxide layer may be formed on the fracture surface, and further, a second gate electrode may formed to overlie each such field effect transistor (FET).
The invention furthe
Gates Stephen M.
Scheuerlein Roy E.
McGinn & Gibb PLLC
Underweiser, Esq. Marian
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