Formation of antifuse structure in a three dimensional memory

Details Formation of antifuse structure in a three dimensional memory Formation of antifuse structure in a three dimensional memory

2000-12-22

2003-04-01

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

C365S159000, C365S175000

Reexamination Certificate

active

06541312

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of vertically stacked field programmable nonvolatile memories and methods of fabrication.
2. Discussion of Related Art
In co-pending application Ser. No. 09/560,626, entitled “Three-Dimension Memory Array Method of Fabrication” assigned to the assignee of the present invention, a 3-D memory array is disclosed employing rail-stacks. The rail-stacks in each layer are parallel, spaced-apart lines in the memory which include conductors and a semiconductor region which forms one-half a diode. An antifuse layer such as a silicon dioxide layer separates the rail-stacks in each layer.
As will be seen, the present invention provides an improved method for forming part of this memory which includes the antifuse layer.
It has been known for many years that electrical fields can be enhanced at sharp corners, rough surfaces and the like. Such enhanced electric fields are used to assist in transferring electrical charge through tunneling and avalanche injection. In other instances, the enhanced electric field and the thinner oxide that can result at protrusion, is used to assist in programming an antifuse layer. See U.S. Pat. Nos. 4,099,196; 4,119,995 and 5,915,171.
SUMMARY OF THE INVENTION
The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material.
In the second embodiment of the present invention the array comprises a first plurality of spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric is recessed below the top surface of the semiconductor material. An antifuse material is formed on the top semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor film is formed on the antifuse material.


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“A Novel High-Density, Low-Cost Diode Programmable Read Only Memory,” by de Graaf, Woerlee, Hart, Lifka, de Vreede, Janssen, Sluijs & Paulzen,IEDM-96, beginning at p. 189.

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