Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With polycrystalline semiconductor isolation region in...
Reexamination Certificate
1999-10-22
2004-07-06
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With polycrystalline semiconductor isolation region in...
C257S499000, C257S538000, C257S543000, C257S545000
Reexamination Certificate
active
06759726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacturing of semiconductor components, and more specifically, of power semiconductor components.
2. Discussion of the Related Art
As semiconductor components, and especially semiconductor power components, have more and more complex structures, various components which have to be laterally isolated from one another are now often located on the same semiconductive chip. The case where this isolation is performed by providing isolating walls of a conductivity type opposite to that of the substrate will be considered herein.
In the field of power components, a specific problem arises due to the fact that the isolating walls have to be deep and to cross an entire silicon wafer. Conventionally, these isolating walls are made by opposite drive-ins formed from the upper and lower surfaces of a silicon wafer.
FIG. 1
shows, in cross-section, and
FIG. 2
shows, in top view, a portion of an N-type semiconductive wafer
1
in which are formed isolating walls to delimit a portion
2
of the semiconductive region. The isolating walls are generally made by providing masks
3
having openings
4
and
5
facing the upper and lower surfaces of the semiconductive wafer according to the desired contour of the isolating wall. Then, diffusions of a type opposite to that of the substrate, herein, type P, respectively
6
and
7
, sufficiently deep to join, are formed from these openings.
The forming time of these diffused walls is very long and the processing temperature has to be very high. Thus, wafers which are as thin as possible tend to be used to reduce the duration of this step. In the case of a wafer having a thickness of 200 &mgr;m (A), diffusions having a depth of, for example, 125 &mgr;m, will have to be provided to be sure that the opposite diffusions join properly. With a boron doping in an N-type substrate, this operation requires a thermal processing of 300 hours at 1280° C.
Another disadvantage of forming an isolating wall by diffusion from the upper and lower surfaces is the surface occupied by the obtained wall. Indeed, during a diffusion step, a lateral diffusion substantially occurs at the same rate as the transversal diffusion. Thus, if it is desired to make a diffusion of a 125-&mgr;m depth, this diffusion will also laterally extend over a 125-&mgr;m length. As indicated in
FIG. 1
, if opening
4
has a width on the order of 50 &mgr;m (C), the total width of the isolating wall will be on the order of 300 &mgr;m (B). For a wafer of a 300-&mgr;m (B) thickness, this width would become greater than 500 &mgr;m (0.5 mm),while the width of the area where the isolating walls join in the median plane of the wafer only is of some tens of micrometers.
Such isolating wall dimensions are far from being negligible in practice. Indeed, knowing that a conventional vertical power structure such as that of a thyristor operates with a mean current density of 2 A/mm
2
, a component meant to conduct a current on the order of 2 A will have a surface of 1 mm
2
while an isolating wall surrounding said component will have a surface on the order of 1.56 mm
2
. Thus, the isolating wall occupies more silicon surface than the component itself. A component intended for conducting a current of 10 A will have an active surface of 5 mm
2
and its isolating wall will occupy a surface of 3 mm
2
. The silicon surface increase due to the wall will be, in this case, 60%.
FIGS. 3A
to
3
C are cross-sectional views of a semiconductor substrate illustrating successive steps of formation of another known type of isolating wall and
FIG. 4
shows a top view thereof.
As shown in
FIG. 3A
, in a first step, cylindrical wells
11
are bored in a silicon substrate. With known methods, holes of a diameter from 1 to 5 &mgr;m can be obtained.
As shown in
FIG. 4
, holes
11
are aligned and spaced apart from one another according to the contour of the isolating wall which is desired to be obtained.
In a second step illustrated in
FIG. 3B
, holes
11
are filled with a material
12
which can be used as a source for a dopant of type opposite to that of the substrate. For example, if the substrate is of type N, this dopant may be boron and material
12
may be boron-doped polysilicon. The filling of the holes may be performed by low pressure vapor phase chemical deposition.
In a third step, illustrated in
FIG. 3C
, the wafer is submitted to a thermal processing so that the P-type dopant included in material
12
diffuses from walls of cylindrical holes
11
and this diffusion is carried on until diffused regions
13
of two adjacent holes join.
The obtained result is illustrated as an example in FIG.
4
. It should be noted that thickness w of the obtained isolating wall only depends on the diameter of holes
11
and on the distance between these holes. By choosing, for example, holes of a 5-&mgr;m diameter spaced apart by 20 &mgr;m, a diffusion step providing a diffused region of a 12.5-&mgr;m extension can be performed, that is, the greatest width of the isolating wall will be equal to 5+2×12.5=30 &mgr;m. Those skilled in the art will choose the dimension and the distance between holes according to the diffusion duration that its manufacturing process can admit. It should be noted as an example that the duration required to obtain a diffusion of a 10-&mgr;m length with boron is 10 hours at 1200° C. The thermal processing thus is much less constraining as previously.
Thus, the method of wall creation by boring of holes has, with respect to the diffusion method, the advantage of a smaller bulk. It however has the disadvantage that, in many cases, the isolating wall still has to have a given thickness and a minimum doping level at the locations where the diffusions from two parallel holes join. To solve this problem, systems including several parallel lines of holes have been provided in prior art. However, these systems have the disadvantage of embrittling the silicon wafer and difficult compromises have to be made between the choice of the distance between parallel holes and the choice of the anneal duration.
Thus, each of the above-mentioned prior systems has disadvantages.
SUMMARY OF THE INVENTION
The present invention aims at overcoming one or several of the disadvantages of prior systems.
More specifically, the present invention provides manufacturing efficient isolating walls, having a small useless width only in addition to their useful width, and relatively simple and fast to manufacture.
To achieve these and other objects, the present invention provides a method of manufacturing an isolating wall in a semiconductor substrate of a first conductivity type, including the steps of boring in the substrate separate recesses according to the desired isolating wall contour; filling the recesses with a material containing a dopant of the second conductivity type; performing an anneal step so that regions of the second conductivity type diffused from neighboring recesses join; and forming a first series of recesses from the upper surface and a second series of recesses from the lower surface, the recesses having a substantially rectangular section, the large dimension of which is perpendicular to the alignment of the recesses and a depth smaller than or equal to the half-thickness of the substrate.
According to an embodiment of the present invention, the first and second series of recesses, seen in projection perpendicularly to the substrate plane, are alternated.
According to an embodiment of the present invention, the recesses are formed by dry etch.
The present invention also provides an isolating wall of the second conductivity type in a substrate of a first conductivity type, including lines of recesses filled with a doped material of the second conductivity type and diffused regions of the second conductivity type extending around each recess, with the areas corresponding to two neighboring recesses joining. A first series of recesses extends from the upper surface and a second series of recesses extends
Anceau Christine
Bonnaud Olivier
Pierre Fabien
Fenty Jesse G.
Jackson Jerome
Jorgenson Lisa K.
Morris James H.
STMicroelectronics S.A.
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