Stock material or miscellaneous articles – All metal or with adjacent metals – Composite; i.e. – plural – adjacent – spatially distinct metal...
Reexamination Certificate
2001-04-30
2002-09-10
Jones, Deborah (Department: 1775)
Stock material or miscellaneous articles
All metal or with adjacent metals
Composite; i.e., plural, adjacent, spatially distinct metal...
C257S750000, C257S774000, C427S099300, C427S252000, C438S618000
Reexamination Certificate
active
06447933
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of interconnect, such as copper interconnect for example, within an integrated circuit, and more particularly, to forming an alloy material, such as copper alloy for example, using alternating depositions of a layer of alloy doping element and a layer of bulk material, for use in forming interconnect.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to
FIG. 1
, a cross sectional view is shown of a copper interconnect
102
within a trench
104
formed in an insulating layer
106
. The copper interconnect
102
within the insulating layer
106
is formed on a semiconductor wafer
108
such as a silicon substrate as part of an integrated circuit. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect
102
is typically formed by etching the trench
104
as an opening within the insulating layer
106
, and the trench
104
is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to
FIG. 1
, the insulating layer
106
may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. The low dielectric constant insulating material has a dielectric constant that is lower than that of pure silicon dioxide (SiO
2
) for lower capacitance of the interconnect, as known to one of ordinary skill in the art of integrated circuit fabrication.
Copper may easily diffuse into such an insulating layer
106
, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material
110
is deposited to surround the copper interconnect
102
within the insulating layer
106
on the sidewalls and the bottom wall of the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material
110
is disposed between the copper interconnect
102
and the insulating layer
106
for preventing diffusion of copper from the copper interconnect
102
to the insulating layer
106
to preserve the integrity of the insulating layer
106
.
Further referring to
FIG. 1
, an encapsulating layer
112
is deposited as a passivation layer to encapsulate the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer
112
is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect
102
does not easily diffuse into such a dielectric of the encapsulating layer
112
.
The patent application with Ser. No. 09/844,727 having title Depositing an Adhesion Skin Layer and a Conformal Seed Layer to Fill an Interconnect Opening, and having the same inventors and filed concurrently herewith, describes a process for forming an interconnect with minimized electromigration failure and void formation within the interconnect. This patent application with Ser. No. 09/844,727 is in its entirety incorporated herein by reference.
As described in patent application with Ser. No. 09/844,727, referring to
FIG. 2
, an adhesion skin layer
212
is deposited on the diffusion barrier material
210
, and a conformal seed layer
214
is deposited on the adhesion skin layer
212
. In
FIG. 2
, the diffusion barrier material
210
is the underlying material onto which the adhesion skin layer
212
is deposited. The diffusion barrier material
210
is similar to the diffusion barrier material
110
of FIG.
1
and is deposited onto the dielectric material of the insulating layer
204
which is formed on the semiconductor substrate
208
to surround the interconnect opening
202
.
Referring to
FIG. 3
, the conductive material
216
is plated from the conformal seed layer
214
. The adhesion skin layer
212
is typically comprised of an alloy material such as a copper alloy when the conformal seed layer
214
and the conductive material
216
are comprised of copper. The adhesion skin layer
212
comprised of the alloy material promotes adhesion of the conformal seed layer
214
to the diffusion barrier material
210
.
Alternatively, as also described in patent application with Ser. No. 09/844,727, referring to
FIG. 4
, an adhesion skin layer
222
is deposited on the dielectric material of the insulating layer
204
at the sidewalls and the bottom wall of the interconnect opening. In
FIG. 4
, the dielectric material of the insulating layer
204
is the underlying material onto which the adhesion skin layer
222
is deposited.
A conformal seed layer
224
is deposited on the adhesion skin layer
222
. Referring to
FIG. 5
, the conductive material
226
is plated from the conformal seed layer
224
. The adhesion skin layer
222
is typically comprised of an alloy material such as a copper alloy when the conformal seed layer
224
and the conductive material
226
are comprised of copper. The adhesion skin layer
222
comprised of the alloy material promotes adhesion of the conformal seed layer
224
to the dielectric material of the insulating layer
204
.
In the prior art, when the alloy material, such as copper alloy for example, of the adhesion skin layer
212
or
222
is deposited using a CVD (chemical vapor deposition) process, the underlying material (such as the diffusion barrier material
210
in
FIG. 2
or the dielectric material of the insulating layer
204
in
FIG. 4
) is exposed to fluorine from a fluorine precursor used in the CVD (chemical vapor deposition) process. Fluorine is corrosive to such underlying material and degrades the performance of the integrated circuit.
Thus, a mechanism is desired for forming the alloy material of the adhesion skin layer
212
or
222
, preferably without corroding the underlying material which may be comprised of the diffusion barrier material
210
or the dielectric material of the insulating layer
204
. Corrosion to the underlying material is undesired because corrosion to the underlying material may degrade the adhesion of the interconnect to the underlying material to increase undesired electromigration failure of the interconnect.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, alternating depositions of a layer of alloy doping element and a layer of bulk material are used for forming the alloy material on the
Lopatin Sergey
Wang Pin-Chin C.
Advanced Micro Devices , Inc.
Blackwell-Rudasill Gwendolyn
Choi Monica H.
Jones Deborah
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