Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2011-04-05
2011-04-05
Lebentritt, Michael S (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S757000, C257S767000, C257S787000, C257SE21504, C257SE21525, C257SE21705, C257SE23007, C257SE23069, C257SE23179, C257SE25013
Reexamination Certificate
active
07919845
ABSTRACT:
Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device using at least in part a first minimum dimension lithography. A second die is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die has the second minimum dimension lithography as a smallest lithography used for the forming of the second die. The first die and the second die are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.
REFERENCES:
patent: 5585282 (1996-12-01), Wood et al.
patent: 5696031 (1997-12-01), Wark
patent: 5729894 (1998-03-01), Rostoker et al.
patent: 6071754 (2000-06-01), Wark
patent: 6140149 (2000-10-01), Wark
patent: 6399416 (2002-06-01), Wark
patent: 6500760 (2002-12-01), Peterson et al.
patent: 6501165 (2002-12-01), Farnworth et al.
patent: 7064579 (2006-06-01), Madurawe
patent: 7068072 (2006-06-01), New et al.
patent: 7075175 (2006-07-01), Kazi et al.
patent: 7091598 (2006-08-01), Fujita et al.
patent: 7132311 (2006-11-01), Akiba et al.
patent: 7301234 (2007-11-01), Lee
patent: 7501696 (2009-03-01), Koyama et al.
patent: 7609561 (2009-10-01), Cornwell et al.
patent: 2002/0066956 (2002-06-01), Taguchi
patent: 2004/0178819 (2004-09-01), New
patent: 2005/0007147 (2005-01-01), Young
patent: 2006/0237835 (2006-10-01), Fujita et al.
patent: 2007/0001168 (2007-01-01), Kirby et al.
Tezzaron Semiconductor, FaStack Technology, “FaStack Creates 3D Integrated Circuits”, 3 pages, revised on May 23, 2007, http://www.tezzaron.com/technology/FaStack.htm (printed on Dec. 20, 2007).
Tezzaron Semiconductor, “FaStack Stacking Technology” 1-4 pages, Rev. 1.4, Feb. 2004.
Gupta, et al., entitled “Techniques for Producing 3DICs with High-Density Interconnect”, Tezzaron Semiconductor Corporation, VMIC, 5 pages, Sep. 2004.
Crotty Patrick J.
Karp James
Nance Scott S.
New Bernard J.
Young Steven P.
King John J.
Lebentritt Michael S
Webostad W. Eric
Xilinx , Inc.
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