Format sensitive timing calibration for an integrated circuit te

Details Format sensitive timing calibration for an integrated circuit te Format sensitive timing calibration for an integrated circuit te

1997-09-30

2000-05-09

Brown, Glenn W.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324532, 3241581, G01R 3126

Patent

active

060608986

ABSTRACT:
Each channel of an integrated circuit tester includes at least one timing signal generator for producing an output timing signal for triggering various types of test events carried out by the tester channel. At the start of each cycle of a test, each timing signal generator receivies input timing data referencing a time at which a test event is to occur and also receives input format data indicating the format of that test event. Each timing signal generator then generates its output timing signal before the event time referenced by the timing data with a lead time selected by the input format data. Each timing signal generator may be independently calibrated such that the format data always selects the appropriate lead time for the event to be triggered so that each type of event occurs at the time indicated by the input timing data regardless of the nature of the event being triggered.

REFERENCES:
patent: 5225775 (1993-07-01), Sekino
patent: 5917834 (1999-06-01), Arkin

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