Format converter

Details Format converter Format converter

2000-06-30

2002-08-06

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

Reexamination Certificate

active

06429794

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a deserializer and components therefor, including format converters.
BACKGROUND OF THE INVENTION
Of late, for some versions of the serial physical layer of the EEE 10 Gbit/s Ethernet standard, a new 66-bit block code has been suggested. At the receiver, the serial data is first de serialized to a sequence of 16 parallel bits which are not aligned with any block or framing structure. Each 66-bit block starts with a 2-bit prefix, a pair of complementary bits to indicate either regular data or control information in the next 8 scrambled bytes. Equal bits in the prefix are a violation of the coding rules. Such violations might originate from transmission errors. The pair of complementary bits is also used to find the 66-bit block boundaries, since any other pair in scrambled data will not have complementary bits at 66-bit intervals over an extended range such as 64 66-bit blocks.
A need has been recognized in connection with addressing the issues described above in an efficient and effective manner.
SUMMARY OF THE INVENTION
In accordance with at least one presently preferred embodiment of the present invention, in the context described heretofore, block boundaries are found with a modest amount of circuitry. Further, the conversion from a 16-bit block format to a 66-bit block format is undertaken via register transfers between registers of modest size. Whereas one might normally be inclined to seek a solution based on the least common multiple between 16 and 66 (which is 16×11×3=528), and use a register of that size, the present invention broadly contemplates enabling the use of a register of considerably smaller size but with similar effect.
A format converter in which the data input is a 16 bit wide interface. The circuit finds the 66-bit coding block boundaries. In one embodiment, a circuit presents the 66-bit data blocks at the output in an aligned format. The circuit relies on control inputs from a state machine (not described here) which controls the operating mode and to which it delivers status information. (As known in the art, a “state machine” is essentially any logic block with at least one latch with internal feedback to change states). The two main operating modes are the “normal data” mode or the “hunt” mode for the 66-bit block boundaries.
In an exemplary (non-restrictive) application according to at least one embodiment of the present invention, part of a 10.3125 Gbaud 64B/66B version of a deserializer is involved. The data input is a 16 bit wide interface clocked at a 644.53125 MHz rate (103125/16). The circuit finds the 66-bit coding block boundaries. A circuit presents the 66-bit data blocks at the output in an aligned format clocked at 156.25 MHz (10,000/64 or 10,312 5/66).
In one aspect, the present invention provides an apparatus for converting data, the apparatus comprising: an input interface which accepts data having a 16-bit width; a converter which converts the 16-bit width data to data having a 66-bit width in aligned format, and an output interface which outputs the aligned 66-bit width data.
In another aspect, the present invention provides a method for converting data, the method comprising the steps of: accepting data having a 16-bit width; converting the 16-bit width data to data having a 66-bit width in aligned format; and outputting the aligned 66-bit width data.
Furthermore, the present invention provides in another aspect, a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for converting data, the method comprising the steps of: accepting data having a 16-bit width, converting the 16-bit width data to data having a 66-bit width in aligned format; and outputting the aligned 66-bit width data.
For a better understanding of the present invention, together with other and further features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, and the scope of the invention will be pointed out in the appended claims.


REFERENCES:
patent: 6140946 (2000-10-01), Desrosiers

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