Forced substrate test mode for packaged integrated circuits

Details Forced substrate test mode for packaged integrated circuits Forced substrate test mode for packaged integrated circuits

1992-03-20

1993-05-18

Nguyen, Vinh

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, 365201, 371 211, G01R 3102, G11C 700

Patent

active

052124428

ABSTRACT:
An integrated circuit such as an SRAM or DRAM fabricated in a package having a number of external pins includes a plurality of inputs and outputs electrically coupled to the external package pins, an internal substrate that is unconnected to any of the external pins, a test mode indicator circuit having an input coupled to an external pin and an output for providing a test mode signal and a switch responsive to the test mode signal for coupling the substrate to a predetermined voltage. The predetermined voltage can either be ground, or a negative voltage introduced on a pin that is normally set to a logic zero during package level testing. The test mode signal can also be used to disable the on-chip charge pump. The test mode indicator circuit can include a super voltage indicator, an electronic key, or latch circuit in order to receive the test mode indication signal on an existing package pin.

REFERENCES:
patent: 4860261 (1989-08-01), Kreifels et al.
patent: 5023840 (1991-06-01), Tobita
patent: 5065091 (1991-11-01), Tobita
patent: 5079763 (1992-01-01), Suwa et al.
patent: 5119337 (1992-06-01), Shimizu et al.

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