Forced bubble insertion scheme

Details Forced bubble insertion scheme Forced bubble insertion scheme

2005-03-28

2010-06-08

Shah, Chirag G (Department: 2477)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C370S395400, C370S458000, C711S123000, C711S125000

Reexamination Certificate

active

07733854

ABSTRACT:
A network device for processing packets. The network device includes a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting the packet to a destination port. The memory management unit includes a timer for indicating that a free space should be created on a bus slot between the memory management unit and the egress module, wherein the free space is used for transmitting CPU instructions from the memory management unit to the egress module.

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David Robinson, Patrick Lysaght, Gordon McGregor and Hugh Dick, Performance Evaluation of a Full Speed PCI Initiator and Target Subsystem Using FPGAs, 1997, Springer Berlin/Heidelberg, Lecture Notes in Computer Science vol. 1304/1997, p. 42.

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