Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-06-29
2001-11-20
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S712000, C438S720000, C438S721000, C438S723000, C438S724000
Reexamination Certificate
active
06319840
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor device manufacturing, and more particularly to a method of fabricating a metal oxide semiconductor field effect transistor (MOSFET) containing structure in which the bitline contacts are self-aligned to the bitlines, and both the bitlines and bitline contacts are fabricated using line-space resist patterns.
BACKGROUND OF THE INVENTION
In the field of semiconductor device manufacturing, it is well known to couple one area of the device to another area of the device through bitlines and bitline contacts. The bitline contacts are typically formed between MOSFETs in the array device regions and they are configured in such a manner that one end of the bitline contact is in electrical contact with a diffusion region formed in the substrate and the other end of the bitline contact is in electrical contact with the bitline. The bitline, on the other hand, is used to provide electrical contact with other device regions present in the structure, or alternatively, with other devices which are external to the semiconductor device.
Typically, prior art bitlines and bitline contacts are formed utilizing two separate and distinct masking steps.
The first masking step forms the bitline contact between MOSFETs, while a separate and distinct masking step is used in defining the region in which the bitline will be formed. The use of prior art methods for fabricating bitlines and bitline contacts adds extra processing steps and costs to the overall manufacturing process.
Moreover, prior art methods of separately preparing bitlines and bitline contacts do not provide a semiconductor structure in which the bitline contact is significantly self-aligned to the bitline. Instead, the separate masking steps may cause a slight misalignment between the bitline and bitline contact. This slight misalignment provided by prior art methods may lead to increased parasitic capacitance, noise and eventually device failures.
in view of the above problems with prior art processes of separately forming bitlines and bitline contacts, there is a continued need for providing a new and improved method in which the bitlines and bitline contacts can be fabricated from a single masking process in which linespace patterns are used in defining both the bitlines and the bitline contacts.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a post gate stack processing scheme that is capable of forming bitline contacts that are self-aligned with the bitlines.
Another object of the present invention is to provide a post gate stack integration scheme in which the bitlines and the bitline contacts are fabricated utilizing a single masking process wherein only line-space resist patterns are employed.
These and other objects and advantages are achieved in the present invention by utilizing a method in which first and second line-space resist patterns are used in defining both the bitlines and bitline contacts. Proper alignment of the bitlines and bitline contacts is achieved in the present invention by forming the second line-space resist pattern perpendicular to the first line-space resist pattern.
Specifically, the method of the present invention, which achieves all of the above mentioned objects, comprises the steps of:
(a) providing a semiconductor structure having a plurality of patterned gate conductors formed on a surface of a gate dielectric, each of said patterned gate conductors including sidewall spacers formed thereon and being separated by a gap region, said gap region being filled with a dielectric material;
(b) forming an oxide cap layer on said dielectric material;
(c) forming a hard mask on said oxide cap layer;
(d) forming a first photoresist on said hard mask, said first photoresist having a first line-space pattern formed therein;
(e) etching through said first line-space pattern so as to pattern the hard mask and to partially remove said oxide cap layer;
(f) forming a second photoresist on said patterned hard mask, said second photoresist having a second line-space pattern formed therein which is perpendicular to said first line-space pattern, whereby a portion of said oxide cap layer between said first and second line-space patterns is exposed;
(g) etching through said exposed portion of said oxide cap layer so as to provide an opening to said gate dielectric in a device contact region;
(h) filling said opening with polysilicon;
(i) etching said polysilicon below a top surface of said oxide cap layer so as to form a recessed area in said opening; and
(j) forming a bitline so as to contact said recessed area provided in step (i).
In one embodiment of the present invention, the oxide cap layer is not partially etched in step (e) above. Instead, in this embodiment, the oxide cap layer is partially removed following bitline contact formation. In another embodiment, the polysilicon employed in step (h) above is replaced with another conductive material such as a conductive metal, e.g., W, or a metallic silicide, e.g., WSi
x
.
REFERENCES:
patent: 5670404 (1997-09-01), Dai
patent: 5936272 (1999-08-01), Lee
patent: 6214743 (2001-04-01), Oiao
Costrini Gregory
Seitz Mihel
International Business Machines - Corporation
Kunemund Robert
Neff, Esq Daryl K.
Scully Scott Murphy & Presser
Umez-Eronini Lynette T.
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