Folding stage for a folding analog-to-digital converter

Details Folding stage for a folding analog-to-digital converter Folding stage for a folding analog-to-digital converter

1995-07-05

1997-05-27

Williams, Howard L.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341133, H03M 100

Patent

active

056336381

ABSTRACT:
A folding stage for a folding analog-to-digital converter comprising a plurality of consecutive reference terminals for providing ascending different reference voltages; a first summing node, a second summing node and a first output node. A plurality of differentially coupled transistor pairs with each one of the pairs comprising a first transistor having a main current path and a control electrode which is coupled to an input terminal for receiving an input voltage to be folded and a second transistor having a main current path and a control electrode which is coupled to a respective one of the consecutive reference terminals. The main current path of the first transistor of consecutive transistor pairs is coupled alternately to the first summing node and the second summing node, and the main current path of the associated second transistor is coupled alternately to the second summing node and the first summing node. A dummy structure comprising a first current source, a first dummy transistor having a control electrode coupled to the input terminal, a first main electrode connected to the first current source and a second main electrode coupled to one of the first and second summing nodes, a second current source, and a second dummy transistor having a control electrode coupled to a bias voltage terminal, a first main electrode connected to the second current source and a second main electrode coupled to the other of the first and second summing nodes. The dummy structure reduces capacitive error currents in the differential output current which flows in the summing nodes of the folding stage by providing cancelling currents to the summing nodes.

REFERENCES:
patent: 4386339 (1983-05-01), Henry et al.
patent: 5307067 (1994-04-01), Kimura et al.
patent: 5376937 (1994-12-01), Colleran et al.
"An 8-bit 100-MHz Full-Nyquist Analog-to-Digital Converter" by Rudy J. Van de Plassche et al, IEEE Journal of Solid-State Circuits, vol. 23, No. 6, Dec. 1988, pp. 1334-1344.
"An 8-bit Video ADC Incorporating Folding and Interpolation Techniques" by Rob E.J. Van de Grift et al, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 6, Dec. 1987, pp. 944-953.

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