Folding and interpolation analog-to-digital converter

Details Folding and interpolation analog-to-digital converter Folding and interpolation analog-to-digital converter

1999-11-05

2001-08-21

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S159000

Reexamination Certificate

active

06278395

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog-to-digital converter (A/D converter) for converting an analog signal to a digital signal, and particularly to a circuit configuration of an interpolation circuit which is one of its component circuits.
2. Description of the Background Art
The role of interpolation circuits in A/D converters will now be described. The A/D converters include the folding interpolation architecture A/D converter shown in FIG.
15
.
As shown in
FIG. 15
, a reference voltage group
111
includes N (≧2) reference voltages Vref
1
, to Vref
N
, in which the reference voltages Vref
1
to Vref
N
are outputted to the folding circuit
72
in the block B
1
and J (<N) of the reference voltages Vref
1
to Vref
N
are outputted to the comparator group
84
as reference voltages Vrr
1
to Vrr
j
for the block B
2
.
FIG. 16
shows an A/D converter having a resolution of six bits, which is constructed on the basis of the configuration shown in FIG.
15
.
In this architecture, A/D conversion is performed separately in the two circuit blocks B
1
and B
2
. The circuit block B
2
is used to achieve rough A/D conversion to determine higher-order bits in the digital code and the circuit block B
1
is used to achieve detailed A/D conversion to determine lower-order bits in the digital code. The higher-order bits and lower-order bits can be combined in many combinations in that architecture, according to which the numbers of comparators, J and M, in the circuit blocks B
2
and B
1
vary as shown in Table 1. The circuit shown in
FIG. 16
corresponds to the configuration in which J=3, M=16, and N=20 in Table 1.
TABLE 1
FIG. 17
is a circuit diagram showing an example of the internal configuration of the interpolation circuit
73
. The number of reference voltages, N, supplied to the folding circuit
72
changes as shown in Table 1 depending on the configuration of the interpolation circuit
73
. The interpolation circuit of
FIG. 17
corresponds to the fourfold interpolation in Table 1, which generates output signals V
i0
, V
i1
, V
i2
, V
i3
(i=1, 2, 3 . . . ) from ends of the four resistors R
30
provided in series between the applied input voltage V
i
and the input voltage V
(i+1)
(i=1, 2, 3 . . . ). That is to say, the interpolation circuit
73
has the fourfold interpolation function.
Next, operation of the above-described A/D converter will be described mainly about the example of structure shown in FIG.
16
.
The comparators CMP
i
(i=1, 2, 3) in the block B
2
compare an analog input voltage Vin and the respective reference voltages Vrr
i
(i=1, 2, 3) in magnitude, and they output “H” when the analog input signal Vin is larger than the reference voltage Vvv
i
, and “L” when the analog input signal Vin is smaller than the reference voltage Vrr
i
.
The preencoder
85
pre-encodes the outputs (comparison results) of the comparator group
84
to generate encoder control signals SP
j
(j=1, 2, 3, 4).
The encoder
86
determines the higher-order 2-bit digital codes D
5
and D
4
in accordance with the encoder control signals SP. Table 2 below shows the comparator outputs from the comparator group
84
, the preencoder outputs from the preencoder
85
, and the encoder outputs from the encoder
86
, for various magnitude relations among the analog input signal Vin and the reference voltages Vrr
1
to Vrr
3
.
TABLE 2
encoder
Input voltage
comparator outputs
preencoder outputs
outputs
conditions
CMP
3
CMP
2
CMP
1
SP
4
SP
3
SP
2
SP
1
D5
D4
Vin < Vrr
1
L
L
L
L
L
L
H
L
L
Vrr
1
≦ Vin < Vrr
2
L
L
H
L
L
H
L
L
H
Vrr
2
≦ Vin < Vrr
3
L
H
H
L
H
L
L
H
L
Vrr
3
≦ Vin
H
H
H
H
L
L
L
H
H
The folding circuit
72
in the block B
1
performs analog computation on the basis of the analog input signal Vin and the reference voltages Vref
k
(k=1, 2 . . . 20) and transmits four sets of output signal pairs VF
m
and VFB
m
(m=1, 2, 3, 4) (not shown in
FIG. 16
) to the interpolation circuit
73
in the next stage. The output signal VFB
m
is a complementary signal of VF
m
.
The above-stated analog computation performed by the folding circuit
72
has the output characteristics as shown in
FIG. 18
, which generates the output signal pairs VF
n
and VFB
n
(n=1, 2, 3, 4) from the analog input signal Vin and the reference voltages Vref
n
, Vref
n+3
, Vref
n+6
, Vref
n+9
, Vref
n+12
(n=1, 2, 3, 4). The output signal pair VF
n
and VFB
n
are complementary signals as a pair of differential signals.
The interpolation circuit
73
voltage-divides the output signals on the basis of the four signal pairs of the output signals VF
n
and VFB
n
(n=1, 2, 3, 4) from the folding circuit
72
to generate and transfer 16 signal pairs VI
y
and VIB
y
(y=1, 2 . . . 16) (not shown in
FIG. 16
) to the comparator group
74
in the next stage. Table 3 shows the relation between the signal pairs VF
n
and VFB
n
and VI
y
and VIB
y
.
TABLE 3
k
VI
k
VIB
k
1
VF
1
VFB
1
2
VF
1
× 3/4 + VF
2
× 1/4
VFB
1
× 3/4 + VFB
2
× 1/4
3
VF
1
× 1/2 + VF
2
× 1/2
VFB
1
× 1/2 + VFB
2
× 1/2
4
VF
1
× 1/4 + VF
2
× 3/4
VFB
1
× 1/4 + VFB
2
× 3/4
5
VF
2
VFB
2
6
VF
2
× 3/4 + VF
3
× 1/4
VFB
2
× 3/4 + VFB
3
× 1/4
7
VF
2
× 1/2 + VF
3
× 1/2
VFB
2
× 1/2 + VFB
3
× 1/2
8
VF
2
× 1/4 + VF
3
× 3/4
VFB
2
× 1/4 + VFB
3
× 3/4
9
VF
3
VFB
3
10
VF
3
× 3/4 + VF
4
× 1/4
VFB
3
× 3/4 + VFB
4
× 1/4
11
VF
3
× 1/2 + VF
4
× 1/2
VFB
3
× 1/2 + VFB
4
× 1/2
12
VF
3
× 1/4 + VF
4
× 3/4
VFB
3
× 1/4 + VFB
4
× 3/4
13
VF
4
VFB
4
14
VF
4
× 3/4 + VFB
1
× 1/4
VFB
4
× 3/4 + VF
1
× 1/4
15
VF
4
× 1/2 + VFB
1
× 1/2
VFB
4
× 1/2 + VF
1
× 1/2
16
VF
4
× 1/4 + VFB
1
× 3/4
VFB
4
× 1/4 + VF
1
× 3/4
As shown in Table 3, for example, while VI
1
is equal to VF
1
, VI
2
is the voltage which is most close to VF
1
among the four fractions of the voltage range of VF
1
and VF
2
(VI
2
=VF
1
×¾+VF
2
×¼), and VI
3
is the middle voltage among the four fractions of the voltage range of VF
1
and VF
2
(VI
3
=VF
1
×½+VF
2
×½).
The comparators CMPD
y
(y=1, 2 . . . 16) in the comparator group
74
compare the signal pairs VI
y
and VIB
y
in magnitude. They output “H” when the signal VI
y
is larger than the signal VIB
y
and “L” in the opposite case.
The preencoder
75
generates encoder control signals SPD
y
(y=1, 2 . . . 16) on the basis of the outputs of the comparator group
74
(not shown in FIG.
16
).
The encoder
76
determines and outputs the lower-order four-bit digital codes D
3
, D
2
, D
1
, D
0
according to the encoder control signals SPD.
Tables 4 to 6 show the comparator outputs from the comparator group
74
the preencoder outputs from the preencoder
75
, and the encoder outputs from the encoder
76
, for part of the conditions of the magnitude relation among the analog input signal Vin and the reference voltages Vref
k
.
TABLE 4
C1 = Vref
2
≦ Vin < Vref
2
× 3/4 + Vref
3
× 1/4
C2 = Vref
2
× 3/4 + Vref
3
× 1/4 ≦ Vin < Vref
2
× 1/2 + Vref
3
× 1/2
C3 = Vref
2
× 1/2 + Vref
3
× 1/2 ≦ Vin < Vref
2
× 1/4 + Vref
3
× 3/4
C4 = Vref
2
× 1/4 + Vref
3
× 3/4 ≦ Vin < Vref
3
C5 = Vref
3
≦ Vin < Vref
3
× 3/4 + Vref
4
× 1/4
C6 = Vref
3
× 3/4 + Vref
4
× 1/4 ≦ Vin < Vref
3
× 1/2 + Vref
4
× 1/2
C7 = Vref
3
&tim

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