Folded logic gate

Details Folded logic gate Folded logic gate

1984-10-31

1986-06-03

Edlow, Martin H.

357 232, 357 237, 357 239, 357 46, 357 15, H01L 2980, H01L 2978, H01L 2702, H01L 2956

Patent

active

045933006

ABSTRACT:
An FET logic gate structure includes two semiconductor layers separated by an insulator. An enhancement mode switching FET is formed in the top semiconductor layer, and a load element is formed in the bottom semiconductor layer. The insulator layer separates and capacitively couples the switching element and the load element so that the switching element acts as a gate for the load element and the load element acts as a second gate of the switching element. An input is connected to the gate of the switching element. The drain of the switching element, the source of the load element, and the output of the folded logic gate are connected together. The logic gate structure exhibits very low power consumption in stable states, high speed and large output voltage swings.

REFERENCES:
patent: 4476475 (1984-10-01), Naem et al.
patent: 4502202 (1985-03-01), Malhi
patent: 4554572 (1985-11-01), Chatterjee
Garnache, "Complimentary FET Memory Cell", IBM Technical Disclosure Bulletin, vol. 18, No. 12, May 1976, pp. 3947-3948.
Cirillo, N. C., Jr. et al, "Self-Aligned Modulation-Doped (Al,Ga)As/GaAs Field-Effect Transistors," IEEE Electron Device Letters, vol. EDL-5, No. 4, Apr. 1984.
Shur, M. S., "Low Field Mobility, Effective Saturation Velocity and Performance of Submicron GaAs MESFETs," Electronic Letters, vol. 18, No. 21, Oct. 14, 1982.
Eden, Richard C. et al, "The Prospects for Ultrahigh-Speed VLSI GaAs Digital Logic," Journal of Solid State Circuits, vol. SC-14, No. 2, Apr. 1979.

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