Folded addressing method for memory architectures

Details Folded addressing method for memory architectures Folded addressing method for memory architectures

2000-05-26

2002-04-09

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

C365S230020, C365S230030, C711S202000

Reexamination Certificate

active

06370076

ABSTRACT:

TECHNICAL FIELD
This invention relates to an architecture for memory organization, and more specifically, for a method and architecture using a folded addressing method.
BACKGROUND OF THE INVENTION
Designers of Very Large Scale Integrated (VLSI) electronic circuits are increasingly pressed to reduce costs and development time. This is particularly true for microcontroller and microprocessor designs. In order to optimize substrate usage and minimize design cycle times, a layout plan of an Integrated Circuit (IC) is often constrained to have a fixed topology like the one shown in FIG.
1
.
FIG. 1
shows a layout view of a typical IC
10
. A central bus
20
carries signal interconnections within the IC
10
. Signals are generated and received by a generic microprocessor
30
, peripheral circuits
32
, and memory circuits
34
.
For a fast assembly of a complex device like the one depicted in
FIG. 1
, it is essential that all blocks are physically designed to have the same height, as shown by the fixed height arrows
36
on the right. In this way, a library of predefined macros or layouts can be designed and made available for a wide range of specific applications, allowing the complete IC
10
to be put together easily, e.g. by software, and with highest silicon utilization.
It is generally easy to shape the physical dimensions of digital and analog peripherals such that one side is at a fixed height. On the contrary, memory blocks introduce specific problems. In fact, for each possible memory function, there is a variety of configurations that can be used in a design.
Although the memory width, or parallelism, which is the number of bits that can be loaded into/from the memory in parallel, N
B
, is generally fixed for a given IC architecture, the memory depth, which is the number of different locations independently addressable, or words N
W
varies with target applications and marketing strategies. It is therefore necessary to implement memory architectures that can expand in the direction of expandable arrows
38
in the memory circuits
34
of FIG.
1
. This expansion allows the memory circuits
34
to be specifically designed to match the memory needs of the peripheral circuits
32
and the generic processor
30
when designing the IC
10
.
For efficiency reasons, memory blocks are designed with a bi-dimentional decoding scheme. In all but very small memory blocks, the input address is decoded by two separate sub-circuits. The word decoder selects a physical row out of the number of Rows N
R
in a memory circuit. On each row, N
M
memory words are allocated. A column multiplexer (or mux) then selects one out of the N
M
words and routs it to the data I/O circuitry.
N
R
=N
W
/N
M
Number of physical rows in the memory matrix  1)
N
C
=N
M
×N
B
Number of physical columns in the memory matrix  2)
The addressing space defined by N
W
must be continuous. If there are voids or holes in the address space, i.e., inputs between address=0 and address=N
W
corresponding to no physical location, all external subsystems accessing the memory block would have to perform complex processing to guarantee proper data storage and/or retrieval around the voids, which is not acceptable.
Usually, best performances, lowest power consumption, and highest memory density are achieved for N
R
≈N
C
, or a generally square architecture where the number of rows is roughly equal to the number of columns. This implies (from equation 2) that optimal configurations are those for which
N
M
≈N
R
/N
B
N
B
generally equal to or greater than 8  3)
Because of equation 3, there are generally many more address bits devoted to word decoding than are used for column multiplexing. In order to enlarge the overall memory depth variation, it is the word decoder that has to vary in the direction of the expandable arrows
38
in the memory circuits
34
of
FIG. 1
, while the column mux must remain fixed. In other words, memory circuits
34
have to be placed in
FIG. 1
with the matrix rotated 90°, making rows physically vertically oriented, and columns physically horizontally oriented.
In order to satisfy the addresses space continuity, the most significant address bits decode one out of N
R
rows and the least significant address bits select one out of N
M
words. Moreover, to preserve address space continuity, the number of words on each row (N
M
) has to be a power of two, or
N
M
=2
m
m=
1,2,3,  4)
So the first row allocates all the memory words (M
W
) numbered from 0 to 2
m
−1, with no voids, the second row consists of words 2
m
to 2
m
+1 −1, etc. If it is assumed a memory cell is designed for highest density and its dimension in the direction of the fixed height arrows
36
in
FIG. 1
is h
c
, then the height (H) of the memory block can only be:
H=N
C
×h
c
=N
B
×2
m
×h
c
m
=1,2,3,  5)
Generally, the values of H obtained through equation 5 are not optimal for the full IC
10
, because the IC dimensions are mandated by efficiency and reliability specifications that cannot take into account all possible memory architectures. Hence, the need for a memory architecture that can preserve addressing continuity and optimize H to any value dictated by IC product definitions.
Some limited degree of freedom in defining H can be achieved through the so-called remainder technique. Assume the N
M
corresponding to the optimal H is:
2/3
N<N
Mopt
<N N
=2
n
; n
=1, 2, 3  6)
Then, memory rows can be designed (N
Mopt
×N
B
) bits wide, and logically arranged into triplets. In a triplet arrangement, the first memory words are placed on the first row, which has a vertical orientation in the memory circuit
34
of the FIG.
1
. The next N−N
Mopt
words constitute a remainder R
1
and are kept aside. The words N
Mopt
+1 to
2×N
Mopt
are placed in the second row, which is also vertical the memory circuit
34
of FIG.
1
. The next N−N
Mopt
words constitute a remainder R
2
. R
1
and R
2
are allocated on the third row of the triplet, denoted as the remainder row in a triplet arrangement. The next row, which is the fourth, starts a new triplet, and the remainder patterns are repeated until the memory addresses exhausted.
If R
1
+R
2
<N
Mopt
, then the remaining bits to fill the remainder row are left unused, which is very expensive in terms of substrate usage efficiency and cost. Limitations of the remainder method are numerous. The method applicability is limited by equation 6. The column mux can be so complex to require automatic synthesis tools to design the address bits scrambling and unused cell reject logic required by remainder rows. The word decoder is also complicated, as it has to differentiate between the first pair of each row triplet and the remainder row. Because of the points above, the method implies a substantial silicon overhead on memories with small/medium arrays, and a reduction in the performance of the memories.
Regarding the layout of a possible memory block using the remainder method, the entire memory floor plan and layout is affected, so that the memory is not reusable in IC configurations that are different from the one in
FIG. 1
, unless the full silicon and performance overhead of the remainder method is acceptable.
Also, in most cases, the silicon wasted on the unused cells in the remainder row deeply impacts the overall memory density. For instance, if N
Mopt
=¾ N, then the remainder row would leave {fraction (1/3,)} or nearly 10% of the total memory cells unused. This inefficiency is too high for most applications.
Although the remainder method is in principle not limited to triplet arrangement, and can use any n-tuple, the circuit complexity and the area overhead increase unacceptably for sets having 4 or more rows.
Until now, no method or memory architecture has been developed which can simultaneously preserve address continuity while optimizing the height H of a

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