Fold and decimate filter architecture

Details Fold and decimate filter architecture Fold and decimate filter architecture

1991-10-10

1993-11-02

Nguyen, Long T.

Boots, shoes, and leggings

G06F 1531

Patent

active

052589390

ABSTRACT:
Decimation circuitry having a forward shifting data section receiving data samples in order including a plurality of forward decimation registers coupled in-line and providing a forward register output. Each forward decimation register operates as a first-in-first-out (FIFO) register having a decimation depth. A backward shifting data section includes a plurality of backward decimation registers having a decimation depth coupled in-line and providing a backward register output. One of the backward decimation registers which receives data samples in sequence from one of the forward decimation registers can function as both a last-in-first-out (LIFO) and a FIFO register, when a LIFO register, it operates to reverse blocks of data samples wherein the size of each block corresponds to the decimation rate. Each reversed block is then shifted through the backward shifting data section. Each of the other backward decimation registers operates as FIFO register. The decimation circuitry can be used to form a digital filter cascadable into various sizes.

REFERENCES:
patent: 3949206 (1976-04-01), Edwards et al.
patent: 4344149 (1982-08-01), van de Meeberg et al.
patent: 4615026 (1986-09-01), Schiff
patent: 4802111 (1989-01-01), Barkan et al.
patent: 4843581 (1989-06-01), Cupo et al.
Philips Technical Review by J. J. Van Der Kam entitled "A Digital Decimating Filter for Analog-to-Digital Conversion of Hi-Fi Audio Signals", vol. 42, No. 6/7, Apr. 1986, pp. 230-238.
Electronic Components and Applications by D. Janssen, et al. entitled "PCM Codec with On-Chip Digital Filters", vol. 2, No. 4, Aug. 1980, pp. 242-250.
Electronics Letters by E. De Man entitled "Linear Phase Decimation and Interpolation for High-Speed Applications", vol. 24, No. 12, Jun. 9, 1988, pp. 757-759.

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