Fluxless flip chip interconnection

Details Fluxless flip chip interconnection Fluxless flip chip interconnection

2001-03-28

2002-12-17

Talbott, David L. (Department: 2827)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S613000, C438S614000, C228S180210, C228S180220

Reexamination Certificate

active

06495397

ABSTRACT:

COPYRIGHT NOTICE
Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of semi-conductor chip packaging. More particularly, the invention relates to the joining of the semi-conductor chip and a substrate using a flip chip process.
2. Description of the Related Art
Traditionally, semi-conductor chips have been electrically coupled to electrical traces on a substrate via wire interconnects that are soldered on one end to the top area of a chip and soldered to trace pads on the substrate that surround the chip on the other end. These types of interconnects are not particularly space-efficient, requiring area for both the footprint of the chip and a trace pad perimeter. To more efficiently utilize the substrate surface and facilitate smaller chip packages, the flip chip interconnection process was developed. Essentially, the active surface of the semi-conductor chip is flipped over to face the substrate and the chip is soldered directly to trace pads located adjacent to the active surface. The result is a more compact and space-efficient package.
One of the most successful and effective methods of electrically connecting a flipped chip to a substrate utilizes controlled-collapse chip connection technology (C4).
FIG. 1
illustrates the C4 process. First, as shown in box
105
, solder bumps are typically applied to pads on the substrate using any number of suitable processes including plating and vapor deposition. Generally, lead-tin solders having melting points below 200 degrees Celsius are used. Next, in box the solder bumps are re-flowed by heating the solder bumps to a temperature above the solder's melting point, to fully wet the solder bumps to their respective pads. Typically, metal bumps or protrusions having a high lead content are deposited on the corresponding chip pads.
In box
115
, a flux is applied to at least one of the surfaces to be joined. Typically, the flux comprises a vehicle and an activator. The flux vehicle acts to isolate the surface of the solder from the atmosphere during a second re-flow, minimizing the risks of oxidation while the solder is hot and/or molten. The flux vehicle is generally tacky and provides an adhesive force to hold the chip and substrate together prior to the second re-flow. The activator is typically an organic or inorganic acid that removes any oxides or surface films present on the solder facilitating solder wetting of the metallic surfaces to be joined. In box
120
, the flux bearing surfaces of the chip and substrate are placed in contact with each other in general alignment.
Next, as illustrated in box
125
, the second re-flow is performed by heating the chip and substrate package to a temperature above the solder's melting point. The molten solder bumps wet the corresponding metal bumps and the surface tension of the molten solder causes the metal bumps to self-align with each of the corresponding substrate pads. The newly formed interconnects are then cooled to solidify the solder.
Any flux or flux residue is removed from the chip and substrate package in a defluxing operation as indicated in box
130
. This operation will typically include solvent washing the package to remove flux residue. A post-interconnection bake cycle may also be specified to volatilize any remaining solvent or low boiling point flux constituents.
An epoxy under-fill is applied between the active surface of the chip and the top surface of the substrate to surround and support the solder interconnects. Under-filling significantly increases the reliability and fatigue resistance of the package's interconnections. The under-fill helps to more evenly distribute stress caused by thermally induced strains due to the differences in coefficients of thermal expansion (CTE) between the chip and substrate across the entire surface of the chip and substrate. If the gap between the interconnected chip and substrate were not under-filled, the stress would be carried by the relatively thin solder interconnects, often resulting in premature package failure. However, in order for the under-fill to perform properly, it must be well-adhered to the chip and substrate surfaces. Even a thin film of flux residue can cause premature delamination of a bonded surface, eventually resulting in failure in one or more of the interconnects. Accordingly, one of the great challenges using C4 technology has been to completely remove all flux residues from the package. This has become especially troublesome as the thickness of the gap between the chip and the substrate has decreased.
The total throughput time (TPT), or the time it takes to create a soldered chip, is affected significantly by the time required to remove residues from the protective flux, which can be particularly time-consuming. For instance, chemical defluxing may take minutes while a post-bake to remove any remaining flux or solvent residue may take several hours. Fluxes have been developed that completely volatilize at elevated temperature. However, because the flux is required in the C4 process to hold the chip and substrate together before re-flow, only those fluxes that have volatilization temperature at or above the solder melting point are suitable for use with the C4 process. The small thickness of the gap distance between the chip and the substrate coupled with the flux's high volatilization temperatures, however, make it difficult, if not impossible, to boil off all of the flux residues during the re-flow process or in a subsequent post-bake operation at a temperature slightly below solder melting temperature. The long post-bake times and defluxing operations required to volatize the flux eliminate any opportunity for significant TPT reductions.


REFERENCES:
patent: 5019673 (1991-05-01), Juskey et al.
patent: 5111279 (1992-05-01), Pasch et al.
patent: 5150274 (1992-09-01), Okada et al.
patent: 5299730 (1994-04-01), Pasch et al.
patent: 5410805 (1995-05-01), Pasch et al.
patent: 5438477 (1995-08-01), Pasch
patent: 5508561 (1996-04-01), Tago et al.
patent: 5710071 (1998-01-01), Beddingfield et al.
patent: 5744869 (1998-04-01), Root
patent: 5778913 (1998-07-01), Degani et al.
patent: 5784780 (1998-07-01), Loo
patent: 5816478 (1998-10-01), Kaskoun et al.
patent: 5834366 (1998-11-01), Akram
patent: 5942798 (1999-08-01), Chiu
patent: 6011312 (2000-01-01), Nakazawa et al.
patent: 6051889 (2000-04-01), Shimura
patent: 6087732 (2000-06-01), Chittipeddi et al.
patent: 6111317 (2000-08-01), Okada et al.
patent: 6121689 (2000-09-01), Capote et al.
patent: 6127731 (2000-10-01), Hoffmeyer
patent: 6344234 (2002-02-01), Dalal et al.
patent: 63-208251 (1988-08-01), None
patent: 63-004652 (1988-09-01), None
Pooya Tadayon, Sort Test Technology Development, Intel Corporation. “Thermal Challenges During Microprocessor Testing”.Intel Technology Journal Q3, Aug. 22, 2000.pp. 1-8.
Dory, Takahashi, Kume, Kubota, Seki and Fujiyama, “Simultaneous Chip-Join and Underfill Assembly Technology for Flip-Chip Packaging”. Intel Technology Journal Q3, pp. 1-7, Aug. 22, 2000.
Polka, Chickamenahalli, Chung, Figueroa, Li, Merley, Wood and Zu, “Package-Level Interconnect Design for Optimum Electrical Performance”. Intel Technology Journal Q3, pp. 1-17, Aug. 22, 2000.
Viswanath, Wakharar, Watwe and Lebonheur, “Thermal Performance Challenges from Silicon to Systems”. Intel Technology Journal Q3, pp. 1-16, Aug. 22, 2000.
Nicholas P. Mencinger, Assembly Technology Development and Reliability, Intel Corp. “A Mechanism-Based Methodology for Processor Package Reliability Assessments”. Intel Technology Journal Q3, pp. 1-8, Aug. 22, 2000.
John H. Lau, “Flip Chip Technologies”,1995 (Electronic Packaging and Interconnection Series) (P-5-K2D36). McGraw-Hill Companies Inc. ©1996. pp. 1-5

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