Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-01-27
2003-10-21
Vanderpuye, Kenneth (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S230000
Reexamination Certificate
active
06636523
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to data communication systems, and more particularly, to flow control in a multiport network switch.
BACKGROUND ART
A multiport network switch may be provided in a data communication network to enable data communication between multiple network stations connected to various ports of the switch. A logical connection may be created between receive ports and transmit ports of the switch to forward received frames to appropriate destinations. Based on rules queues containing information on receive frames, a frame forwarding system selectively transfers received frames to a destination station.
A flow control procedure is-used in the network switch for controlling the transfer of data among ports to prevent overload. Conventionally, flow control is performed based on monitoring receive buffers of switch ports. However, to increase the accuracy of flow control, it would be desirable to perform flow control based on monitoring the rules queues in the frame forwarding system.
DISCLOSURE OF THE INVENTION
The invention provides a novel method of flow control in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. The method comprises placing data blocks representing received data packets in a plurality of data queues to be processed by the decision making engine in accordance with a prescribed algorithm to determine a selected transmit port. The plurality of data queues corresponds to the plurality of the receive ports. The data queues are monitored to produce a flow control threshold signal for a selected data queue to indicate a heavy traffic condition of a receive port corresponding to the selected data queue. For example, the flow control threshold signal may indicate that the receive port is close to an overflow condition. The flow control threshold signal may be produced when the content of the selected data queue reaches a preset value.
Preferably, monitoring of a selected data queue may be performed by comparing a write pointer indicating memory locations for writing the data blocks into a selected data queue with a read pointer indicating memory locations for reading the data blocks from the selected data queue.
In accordance with one aspect of the invention, the decision making engine includes a plurality of queuing devices corresponding to the plurality of the receive ports for creating queues of data blocks representing the data packets received by the corresponding receive ports. Logic circuitry is responsive to the plurality of queuing devices for processing the data blocks in accordance with a prescribed algorithm to identify the at least one selected transmit port for each data packet. A flow control circuit is provided for monitoring the queues of data blocks to produce a flow control threshold signal for a selected queue of data blocks. For example, the flow control threshold signal for a selected queue may be produced when the selected queue accumulates a predetermined number of the data blocks.
Preferably, the flow control circuit may comprise a threshold circuit, a write pointer circuit and a read pointer circuit. The flow control circuit may compare a write pointer to a selected queue with a read pointer to the selected queue to determine content of the selected queue.
The write pointer circuit for producing the write pointer may comprise a write pointer selector for selecting the write pointer for the selected queue. The write pointer selector may be controlled by write enabling signal that enables writing the data blocks into the selected queue. The write pointer circuit may further comprise an incrementer/encoder for incrementing and encoding a selected write pointer produced by the write pointer selector.
The read pointer circuit for producing the read pointer may comprise a read pointer selector for selecting the read pointer for the selected queue. The read pointer selector may be controlled by a grant signal that enables reading the data blocks from the selected queue. The grant signal may be produced by a scheduler responsive to a request from a queuing device that holds the selected queue. The read pointer circuit may further comprise an incrementer/encoder for incrementing and encoding a selected read pointer produced by the read pointer selector.
For example, each queuing device may comprise a queue memory array arranged in rows and columns for storing a queue of data blocks. To monitor a data queue, a write row pointer indicating a row for writing the data blocks into a selected queue memory array may be compared with a read row pointer indicating a row for reading the data blocks from the selected queue memory array.
Various objects and features of the present invention will become more readily apparent to those skilled in the art from the following description of a specific embodiment thereof, especially when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5493566 (1996-02-01), Ljungberg et al.
patent: 5515376 (1996-05-01), Murthy et al.
patent: 5787073 (1998-07-01), Ikeda
patent: 5828653 (1998-10-01), Goss
patent: 5841773 (1998-11-01), Jones
patent: 6091709 (2000-07-01), Harrison et al.
patent: 6118761 (2000-09-01), Kalkunte et al.
Lau Michael Vengchong
Merchant Shashank C.
Advanced Micro Devices , Inc.
Vanderpuye Kenneth
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