Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network
Reexamination Certificate
2008-05-27
2008-05-27
Jagannathan, Melanie (Department: 2619)
Multiplex communications
Data flow congestion prevention or control
Control of data admission to the network
C370S231000, C370S237000, C370S248000, C370S253000, C370S413000, C370S419000, C370S429000, C370S466000, C709S235000
Reexamination Certificate
active
10325114
ABSTRACT:
A networking/communication chip having a receiving buffer or FIFO whereby it receives data from a data source across a network and transfers the data to a host system. The memory in the host system acts as a logical extension of the receiving buffer in the chip; in this way, the host system controls the flow of data from the source, rather than the control flow being based on the capacity of the receiving buffer in the networking/communication chip. The networking/communication chip may be a controller, such as a 10 Gigabit Ethernet controller, wherein data received from the source in one protocol is transformed to a second protocol input to the host. If either or both the networking/communication chip or the host system is/are made of FPGAs, it/they can be reprogrammed to disable the flow control in the networking/communication chip and enable flow control in the host system. Data flow is enhanced because memory in the host system typically is much larger than memory in the networking/communication chip.
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“Flow Control in IXF1010 and IXF1110 10-port Gigabit Ethernet Media Access Controller”, Intel Application Note, Order No. 250236-001, pp. 1-8, Apr. 28, 2002.
Jagannathan Melanie
LSI Logic Corporation
Maiorana P.C. Christopher P.
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