Floating pointing arithmetic operation system

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36471503, G06F 738

Patent

active

053031741

ABSTRACT:
In a floating point arithmetic addition/subtraction system which is configured to receive a pair of input operands of floating point data including its mantissa part expressed in an absolute value so as to execute an addition/subtraction and which includes a mantissa adder, a normalizing shifter, an exponent part updater and a bit position decoder, integer data expressed in a 2's complement is supplied as one of the pair of input operands, and the integer data is converted into an absolute value by using the mantissa adder. Thereafter, the bit position of the obtained absolute value is modified by using the normalizing shifter so as to give a mantissa part, and a value of an exponent part is generated by using the updater and the bit position decoder.

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patent: 4758974 (1988-07-01), Fields et al.
patent: 5027308 (1991-06-01), Sit et al.
patent: 5063530 (1991-11-01), Ishikawa
patent: 5146419 (1992-09-01), Miyoshi et al.

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