Floating point unit using combined multiply and ALU functions

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G06F 748

Patent

active

048666521

ABSTRACT:
A method and apparatus for combining the multiply and ALU functions for floating point numbers to enable the completion of a multiply-accumulate operation in a shorter time. The multiplied fraction is left in sum and carry form and is provided in this form to the ALU, eliminating the CP adder from the multiplier. The normalization of the fraction and the corresponding changes to the exponent in the multiplier are also eliminated. The ALU can combine the sum and carry of the product fraction simultaneously if the exponents are sufficiently similar. Otherwise, the sum and carry of the fraction product is combined first and compared with the new fraction, with the smaller of the fractions being right shifted prior to their combination.

REFERENCES:
patent: 4760551 (1988-07-01), Yokomizo et al.

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