Floating point unit power reduction scheme

Details Floating point unit power reduction scheme Floating point unit power reduction scheme

2005-07-26

2005-07-26

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06922714

ABSTRACT:
A system and method for reducing the power consumption of a floating point unit of a processor wherein the processor iteratively performs floating point calculations based upon one or more input operands. The exponential value of a floating point is precalculated within an iterative loop through a superscalar instruction buffer resident on the processor that holds at least 3 iterations of the largest single cycle iteration possible on the processor, and the precalculated exponent value is used to generate a bit mask that enables a minimal number of fractional data flow bits. Alternately, a look-ahead can be used to obtain the exponent value from at least two subsequent iterations of the loop.

REFERENCES:
patent: 5923871 (1999-07-01), Gorshtein et al.
patent: 6487575 (2002-11-01), Oberman

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