Floating point unit interface

Details Floating point unit interface Floating point unit interface

1985-11-14

1991-12-03

Heckler, Thomas M.

G06F 1300

Patent

active

050704753

ABSTRACT:
A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.

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patent: 4395758 (1983-07-01), Helenius et al.
patent: 4484259 (1984-11-01), Palmer et al.
patent: 4509116 (1985-04-01), Lackey et al.
patent: 4547849 (1985-10-01), Louie et al.

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