Floating point unit having a unified adder-shifter design

Details Floating point unit having a unified adder-shifter design Floating point unit having a unified adder-shifter design

1998-04-30

2000-11-14

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708209, G06F 750, G06F 501

Patent

active

06148315&

ABSTRACT:
An improved floating point unit is disclosed. The floating point unit includes a combined adder-shifter that operates to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand. The combined adder-shifter includes an adder portion that operates to generate a number of sum bits for exponent difference between the two floating point operands. The adder portion favors generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits. The combined adder-shifter also includes a shifter portion that operates to shift the mantissa portion of the at least one floating point operand in accordance with the sum bits.

REFERENCES:
patent: 5016209 (1991-05-01), Ikeda et al.
patent: 5166898 (1992-11-01), Ishihara
patent: 5303174 (1994-04-01), Okamoto
patent: 5726926 (1998-03-01), Makino
patent: 5790445 (1998-08-01), Eisen et al.
patent: 5954790 (1999-09-01), Wong

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