Floating point unit for multiple data architectures

Details Floating point unit for multiple data architectures Floating point unit for multiple data architectures

2001-01-18

2004-12-07

Do, Chat C. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S200000, C708S160000

Reexamination Certificate

active

06829627

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to computer systems and architecture, and more particularly, to a computer system having a floating point unit (“FPU”) for supporting multiple floating point architectures.
Computer software is typically designed to utilize one of several floating point architectures, such as either IEEE Binary Floating Point Standard 754-1985 (“IEEE-754”), or IBM®-S/390® hexadecimal floating point standard. See “Enterprise Systems Architecture/390 Principles of Operation” (Order No. SA22-7201-02, IBM®, 1994); and “IEEE standard for binary floating-point arithmetic, ANSI/IEEE Std 754-1985.”
Software applications that are designed for one floating point architecture may not be compatible with another floating point architecture. However, it is often desirable to run the same application on different hardware platforms supporting different floating point architectures, or to use data generated by an application on one platform with a different application on another platform that supports a different floating point architecture. Moreover, it is often desirable to run applications that are based on different floating point architectures on a single machine. These needs are particularly relevant to multi-tasking environments where task switching between different applications may require using different floating point architectures.
The representation of a floating point number is different between IBM®-S/390® hexadecimal based architecture and IEEE-754 compliant binary architecture. In an IBM®-S/390® hexadecimal architecture format, a floating point number, N
HA
, is represented by
N
HA
=(−1)
S
×16
(Exponent−Hex Bias)
×0.Fraction  (1)
The hexadecimal Exponent field is 7 bits in length for all formats and the Fraction field is 24 bits in length for Short format, 56 bits in length for Long format or 112 bits in length for Extended format. In an IEEE binary architecture format a floating point number, N
BA
, is represented by
N
BA
=(−1)
S
×2
(Exponent−Binary Bias)
×1.Fraction  (2)
The binary Exponent field is 8, 11 or 15 bits in length and the Fraction field is 24, 53 or 113 bits in length for the Single, Double or Double Extended formats, respectively. The values of the exponent biases for the two architectures are also different. In particular, the value of the hexadecimal architecture Exponent Bias is 64 for Short, Long and Extended formats. The value of the binary architecture Exponent Bias is 127 for the Single format, 1023 for the Double format and 16,383 for the Double Extended format.
It is desirable to create an FPU for a computer system that supports multiple floating point architectures. Multiple floating point architecture support should be provided without resorting to duplication of floating point hardware and without sacrificing performance. In addition, such an architecture should be transparent to the greatest extent possible in order to simplify the interaction between the user and the system.
Accordingly, there is a need for a single FPU that supports both a hexadecimal based IBM®-S/390® hexadecimal architecture and an IEEE-754 compliant binary architecture. It is also desirable to create a single floating point unit that supports both architectures efficiently, without sacrificing performance. It would be inefficient in terms of hardware usage to implement two floating point units, one for each format. Some previous attempts converted all binary operands into a hexadecimal-like format and operated internally on just one format. However, performance was sacrificed in these implementations because two additional cycles were required to format binary input into hexadecimal, and then reformat a hexadecimal result into binary. Other previous attempts optimized the data-flow for binary, and converted only the hexadecimal operands into the binary format. However, this penalized hexadecimal operands with format conversion cycles.
SUMMARY OF THE INVENTION
An embodiment of the invention is directed to a computer system with a floating point unit (“FPU”) for supporting multiple floating point architectures. Multiple floating point architectures are supported by an FPU with an internal data-flow format that accommodates formats of each architecture. The system includes a format converter for converting between the internal data flow format and the architected external data types by multiplexing the exponent.
The system includes a floating point unit having an internal data-flow according to an internal floating point format for performing floating point operations. The internal format has a number of exponent bits sufficient to support each of the plurality of floating point architectures and the internal format has a number of fraction bits sufficient to support each of the plurality of floating point architectures.
The system also includes format converters for converting the exponent value of each floating point architecture into the internal floating point format so that a data operand of any of the floating point architectures input to the floating point unit is converted into the internal floating point format for subsequent arithmetic operations, and the result of the operation is converted back into the original floating point architecture by converting the exponent value of the result from the internal floating point format into the original floating point architecture.


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IEEE Standard for Binary Floating-Point Arithmetic, The Institute of Electrical and Electronics Engineers, Inc., Copyright 1985.
Hexadecimal-Floating-Point Instructions, IBM Enterprise Systems Architecture/390, Principles of Operation, Eighth Edition, Jul. 2001.

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