Floating point safe instruction recognition method

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364745, G06F 738

Patent

active

053073010

ABSTRACT:
A safe instruction recognition method and apparatus for use in a pipelined floating-point processor is described. It is based on the examination of the exponents of each operand. A simple symmetric test, applicable to each exponent, is disclosed using the same fixed upper and lower limits. A parallel safe instruction recognition network is described that allows the simultaneous testing of both operand exponent lower and upper limits. All operands declared safe by this method ensure against floating-point processor overflow and underflow exceptions for add, subtract, multiply and divide operations.

REFERENCES:
patent: 4773035 (1988-09-01), Lee et al.
patent: 4788655 (1988-11-01), Nakayama et al.
patent: 4879676 (1989-11-01), Hansen
patent: 5038313 (1991-08-01), Kojima
patent: 5111421 (1992-05-01), Molnar et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Floating point safe instruction recognition method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating point safe instruction recognition method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating point safe instruction recognition method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1716995

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.