Floating point safe instruction recognition apparatus

Details Floating point safe instruction recognition apparatus Floating point safe instruction recognition apparatus

1992-06-10

1993-10-26

Mai, Tan V.

Boots, shoes, and leggings

364745, 3401462, G06F 738, G06F 702

Patent

active

052572161

ABSTRACT:
A safe instruction recognition method and apparatus for use in a pipelined floating-point processor is described. It is based on the examination of the exponents of each operand. A simple symmetric test, applicable to each exponent, is disclosed using the same fixed upper and lower limits. A parallel safe instruction recognition network is described that allows the simultaneous testing of both operand exponent lower and upper limits. All operands declared safe by this method ensure against floating-point processor overflow and underflow exceptions for add, subtract, multiply and divide operations.

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patent: 4879676 (1989-11-01), Hansen
patent: 5038313 (1991-08-01), Kojima
patent: 5111421 (1992-05-01), Molnar et al.

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