Floating point register stack management for CISC

Details Floating point register stack management for CISC Floating point register stack management for CISC

1999-11-29

2003-11-18

Pan, Daniel H. (Department: 2783)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C712S210000, C712S222000, C712S041000, C712S043000, C712S023000, C712S229000, C711S171000

Reexamination Certificate

active

06651159

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microprocessor architecture and, in particular, to floating point register architecture.
2. Discussion of the Related Art
With the advent of more and more different types of computer systems and microprocessors, the number of different instruction sets for such systems continues to increase. Certain existing instruction sets, such as the x86 instruction set developed by Intel Corporation of Santa Clara, Calif. for its family of microprocessors, predominate the computer system market. Thus, by designing new microprocessors having the capability of operating with both an existing instruction set and an instruction set native to the new microprocessor, the value of the new microprocessor increases because the new microprocessor will be able to execute a wider range of applications. Native instructions are instructions that are decoded and executed by the processor directly. Because the x86 instruction set is so widely used for such a large number of applications, a major objective for developers of new microprocessors is to design their microprocessors or central processing units (CPUs) for compatibility with both the x86 instruction set and the computer's native instruction set.
The x86 instruction set is executed by complex instruction set computer (CISC) processors, while native instruction sets are typically executed by reduced instruction set computer (RISC) processors. For applications to run in either or both instruction sets, data and other information in floating point registers should be shared between RISC programs and CISC programs. Floating point numbers include a fraction or mantissa portion and an exponent portion. Formats for floating point data are typically wider than for integer data, e.g., 64 or 80-bit formats for floating point numbers compared to a 32-bit format for integers. CISC processors typically support a wider floating point format of 80 bits, while RISC only provides for a 64-bit format. Therefore, because of the different length formats for CISC and RISC processors, or similarly between x86 and native instruction sets, sharing data between the two data formats is not easily accomplished.
One way to share data and other information is to store the data in a register within the CPU before switching to the alternate instruction set and then to read the register by the instruction set. However, this requires that the registers be readable by either instruction set and that the instruction sets be extended to provide instructions to read the additional registers, thereby increasing the complexity and size of the CPU.
Another way to share data is to provide two sets of register stacks for the CPU, one set for the use of x86 instructions and a second set for the use of native instructions. Register stacks reside on the CPU die, which has a limited space available for registers. Thus, any additional registers require increasing the size of the CPU die or deleting functions of the CPU to free up die space for the additional stack. As a result, using two sets of register stacks increases size and cost and/or reduces efficiency of the computer system.
Accordingly, it is desired to have register stacks which support both CISC (e.g., x86 instructions) and RISC (e.g., native instructions) architectures for a dual-instruction-set CPU without the problems discussed above with respect to conventional methods.
SUMMARY OF THE INVENTION
According to the present invention, a floating point register stack combines pairs of data registers to form wider data registers such that different types of instruction sets with wider data formats can be supported. Thus, the resulting register stack can support both the processor's native instruction set and a wider instruction set, such as the x86 instruction set. Instructions map 80-bit x86 instructions into two 64-bit native general purpose registers to provide the required functions of an x86 floating point stack, which allows the processor greater flexibility to run an greater number of operations and applications.
The present invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.


REFERENCES:
patent: 3707725 (1972-12-01), Dellheim
patent: 5685009 (1997-11-01), Blomgren et al.

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