Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2006-02-07
2006-02-07
Chaki, Kakali (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S497000
Reexamination Certificate
active
06996596
ABSTRACT:
Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes an operand processing section and an operand flush section. For each floating-point operation, the operand processing section receives and processes one or more input operands to provide a preliminary result. The operand flush section determines whether the preliminary result falls within one of a number of ranges of values and sets the preliminary result to one of a number of set values if the preliminary result falls within one of the ranges. In a specific implementation, a first range of values is defined to include values greater than zero and less than half of a minimum normalized number (i.e., 0<|y|<+amin/2), a second range of values is defined to include values equal to or greater than +amin/2 and less than +an, (i.e., amin/2≦|y|<amin), and the preliminary result is set to zero if it falls within the first range and to +aminor −amin(depending on the sign bit) if it falls within the second range.
REFERENCES:
patent: 4156279 (1979-05-01), Wilhite
patent: 4511990 (1985-04-01), Hagiwara et al.
patent: 4839846 (1989-06-01), Hirose et al.
patent: 4866652 (1989-09-01), Chu et al.
patent: 4879676 (1989-11-01), Hansen
patent: 5025407 (1991-06-01), Gulley et al.
patent: 5038313 (1991-08-01), Kojima
patent: 5159665 (1992-10-01), Priem et al.
patent: 5185713 (1993-02-01), Kobunaya
patent: 5206823 (1993-04-01), Hesson
patent: 5220524 (1993-06-01), Hesson
patent: 5257216 (1993-10-01), Sweedler
patent: 5278949 (1994-01-01), Thayer
patent: 5341321 (1994-08-01), Karp et al.
patent: 5357599 (1994-10-01), Luken
patent: 5359548 (1994-10-01), Yoshizawa et al.
patent: 5367650 (1994-11-01), Sharangpani et al.
patent: 5392228 (1995-02-01), Burgess et al.
patent: 5420966 (1995-05-01), Silverbrook
patent: 5420971 (1995-05-01), Westerink et al.
patent: 5511016 (1996-04-01), Bechade
patent: 5517438 (1996-05-01), Dao-Trong et al.
patent: 5530663 (1996-06-01), Garcia et al.
patent: 5550767 (1996-08-01), Taborn et al.
patent: 5550768 (1996-08-01), Ogilvie et al.
patent: 5553015 (1996-09-01), Elliott et al.
patent: 5602769 (1997-02-01), Yu et al.
patent: 5619198 (1997-04-01), Blackham et al.
patent: 5631859 (1997-05-01), Markstein
patent: 5652875 (1997-07-01), Taylor
patent: 5671170 (1997-09-01), Markstein et al.
patent: 5671401 (1997-09-01), Harrell
patent: 5701442 (1997-12-01), Ronen
patent: 5720019 (1998-02-01), Koss et al.
patent: 5726927 (1998-03-01), Wolrich et al.
patent: 5729724 (1998-03-01), Sharangpani et al.
patent: 5764555 (1998-06-01), McPherson et al.
patent: 5768170 (1998-06-01), Smith
patent: 5774709 (1998-06-01), Worrell
patent: 5790827 (1998-08-01), Leung
patent: 5793661 (1998-08-01), Dulong et al.
patent: 5805486 (1998-09-01), Sharangpani
patent: 5809294 (1998-09-01), Ando
patent: 5815695 (1998-09-01), James et al.
patent: 5847979 (1998-12-01), Wong et al.
patent: 5848269 (1998-12-01), Hara
patent: 5852726 (1998-12-01), Lin et al.
patent: 5862066 (1999-01-01), Rossin et al.
patent: 5867682 (1999-02-01), Witt et al.
patent: 5880983 (1999-03-01), Elliott et al.
patent: 5880984 (1999-03-01), Burchfiel et al.
patent: 5889690 (1999-03-01), Arakawa
patent: 5892698 (1999-04-01), Naffziger
patent: 5901076 (1999-05-01), Lynch
patent: 5923577 (1999-07-01), Wong et al.
patent: 5928316 (1999-07-01), Wong et al.
patent: 5953241 (1999-09-01), Hansen et al.
patent: 5977987 (1999-11-01), Duluk, Jr.
patent: 5982380 (1999-11-01), Inoue et al.
patent: 5995122 (1999-11-01), Hsieh et al.
patent: 5996066 (1999-11-01), Yung
patent: 5999960 (1999-12-01), Gerwig et al.
patent: 6035316 (2000-03-01), Peleg et al.
patent: 6065115 (2000-05-01), Sharangpani et al.
patent: 6115729 (2000-09-01), Matheny et al.
patent: 6169554 (2001-01-01), Deering
patent: 6175370 (2001-01-01), Kunimatsu
patent: 6175851 (2001-01-01), Iourcha et al.
patent: 6175907 (2001-01-01), Elliott et al.
patent: 6199089 (2001-03-01), Mansingh
patent: 6249798 (2001-06-01), Golliver et al.
patent: 6268875 (2001-07-01), Duluk, Jr. et al.
patent: 6269385 (2001-07-01), Han et al.
patent: 6275838 (2001-08-01), Blomgren et al.
patent: 6285378 (2001-09-01), Duluk, Jr.
patent: 6285779 (2001-09-01), Lapidous et al.
patent: 6298365 (2001-10-01), Dubey et al.
patent: 6401108 (2002-06-01), Van Nguyen
patent: 6426746 (2002-07-01), Hsieh et al.
patent: 6510446 (2003-01-01), Fukagawa
patent: 6535898 (2003-03-01), Yuval
patent: 6581087 (2003-06-01), Inoue et al.
patent: 6631392 (2003-10-01), Kelley et al.
patent: 6697832 (2004-02-01), Kelley et al.
patent: 6714197 (2004-03-01), Thekkath et al.
patent: 6732259 (2004-05-01), Thekkath et al.
David Stevenson et al. IEEE Standard for Binary Floating-Point Arithmetic, Jul. 26, 1985, pp. 1-19.
TMS32010 User's Guide, Texas Instruments, 1983, p. 1183.
AltiVec™ Technology Programming Environments manual, Preliminary REV 0.2, May 1998, pp. 4-16 thru 4-19 (4 pages total).
Heinrich, Joe, MIPS R4000 Microprocessor User's manual, Second Edition, MIPS Technologies, 1994, pp. 154-155, 157, 159, 161, 168, 170-171, B-13, B17, B-19, B-21, B-23, B-27, B-38, B-40 and B-62 (19 pages total). Note: The page count of this document was cited in an International Search Report from a PCT Application.
3DNow!™ Technology manual, Advanced Micro Devices, 1998, pp/ i-x and 1-62 (72 pages total).
Higaki et al., Four-Way VLIW Geometry Processor for 3D Graphics Applications, Dec. 1, 1999, p. 39-47.
Hughes, PL.I Programming, 1973, John Wiley & Sons, pp. 5, 15-16, 74-75, 188-189, 217, 411-416, 423-424, and 689-690.
Higaki et al., “A 2.5 GFLOPS 6.5 Million Polygons per Second 4-Way VLIW Geometry Processor with SIMD Instructions and a Software Bypass Mechanism,” IEEE International Solid-State Circuits Configuration, 1999.
Ito, Masayuki et al., “Efficient Initial Approximation for Multiplicative Division and Square Root by Multiplication with Operand Modification”, IEEE Transactions on Computers, vol. 46, No. 4, Apr. 1997, pp. 495-498.
Diefendorff, Keith et al., “AltiVec Extension to PowerPC Accelerates Media Processing,” IEEE Micro, pp. 85-95, Mar.-Apr. 2000.
Kubosawa et al., “A 2.5-GFLOPS, 6.5 Million Polygons per Second, Four-Way VLIW Geometry Processor with SIMD Instructions and a Software Bypass Mechanism,” IEEE Journal of Solid-State Circuits, vol. 34, No. 11, pp. 1619-1626, Nov. 1999.
Kubosawa et al., “Four-Way VLIW Geometry Processor for 3D Graphics Applications,” Fujitsu Sci. Tech. J., 36, 1, pp 39-47, Jun. 2000 (manuscript received Dec. 1, 1999).
“MIPS Extension for Digital Media with 3D,” MIPS Technologies, Inc., pp. 1-26, Dec. 27, 1996.
Thekkath et al., “An Architecture Extension for Efficient Geometry Processing,” pp. 1-23, Presented at Hot Chips 11, A Symposium of High-Performance Chips, Stanford Univ. (Aug. 1999) (submitted for conference review Jul. 14, 1999).
Uhler, M., “Optimizing Game Applications for the MIPS RISC Architecture,” 1999 Computer Game Developer's Conference, San Jose, CA, 14 pages (Mar. 1999) (submitted for conference review on Feb. 12, 1999).
Uhler, M., “Optimizing Game Applications for MIPS RISC Architecture,” 1999 Computer Game Developer's Conference, San Jose, CA, slides 1-22 (Mar. 1999).
Kubosawa, H. et al., “A 2.5-GFLOPS, 6.5 Million Polygons per Second, Four-Way VLIW Geometry Processor with SMID Instructions and a Software Bypass Mechanism,” IEEE Journal of Solid-State Circuits, IEEE, vol. 34, No. 11, pp. 1619-1626, (Nov. 1999) (appears to correspond to document AR1, Higaki, N. et al.).
Rice et al, “Multiprecision Division on an 8-Bit Processor,” Computer Arithmetic, 1997 (Proceedings, 13th IEEE Symposium on Jul. 6-9, 1997), pp. 74-81).
Oberman et al., “AMD 3DNow? Technology and K6-2 Microprocessor” (presentation), Proceeding Notebook for Hot Chips 10, Aug. 16-18, 1998 (pp. 245-254).
U
Ho Ying-wai
Jiang Xing Yu
Chaki Kakali
Dinh & Associates
Do Chat
Mips Technologies, Inc.
LandOfFree
Floating-point processor with operating mode having improved... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Floating-point processor with operating mode having improved..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating-point processor with operating mode having improved... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3685308