Floating point processor with internal free-running clock

Details Floating point processor with internal free-running clock Floating point processor with internal free-running clock

1990-10-12

1992-10-06

Mai, Tan V.

Boots, shoes, and leggings

364760, G06F 738

Patent

active

051538482

ABSTRACT:
In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recorded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder (CSA) cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier and divider are pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include two-speed internal clocking for operation and testing, two-node clock stopping and distributed buffering of system clock signals.

REFERENCES:
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4488252 (1984-12-01), Vassar
patent: 4763294 (1988-08-01), Fong
patent: 4773035 (1988-09-01), Lee et al.
patent: 4870608 (1989-09-01), Kametani
patent: 4879676 (1989-11-01), Hansen
patent: 4901267 (1990-02-01), Birman et al.
patent: 4975868 (1990-12-01), Freerlesen
patent: 4996661 (1991-02-01), Cox et al.

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