Floating point processor supporting hexadecimal and binary modes

Details Floating point processor supporting hexadecimal and binary modes Floating point processor supporting hexadecimal and binary modes

1995-03-31

1997-11-11

Kim, Kenneth S.

Boots, shoes, and leggings

364748, 364781, 364784, 395567, 395570, G06F 738

Patent

active

056873590

ABSTRACT:
A computer system having multiple floating point modes and common instructions for each mode in order to implement operations in a mode independent manner. A computer system includes two floating point modes supported by a common set of instructions for implementing operations, said instructions thereby being mode independent. The computer system includes a means for storing information for specifying the current floating point mode; and a floating point unit adapted to execute any one instruction from among the common set of instructions in accordance with the stored rounding mode and the operation associated with said instruction, thereby providing for mode independent operation. In an embodiment of the present invention, the floating point mode is either binary floating point or hexadecimal floating point.

REFERENCES:
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4603323 (1986-07-01), Hassitt et al.
patent: 4675809 (1987-06-01), Omoda et al.

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