Floating-point processor provided with high-speed detector of ov

Details Floating-point processor provided with high-speed detector of ov Floating-point processor provided with high-speed detector of ov

1990-01-31

1991-08-06

Shaw, Dale M.

Boots, shoes, and leggings

364748, 364745, G06F 700, G06F 738

Patent

active

050383132

ABSTRACT:
A processor includes an exception detector for receiving floating-point data on which a rounding operation is to be performed. The exception detector detects whether or not an overflow or an underflow exception occurs in floating-point data without using output floating-point data obtained by performing a rounding operation on the input floating-point data. The exception detector includes a flag indicating the type of rounding operation to be performed and an adder which unconditionally performs a rounding operation by raising a mantissa part of input floating-point data. An exponent detector evaluates an exponent part of the input floating-point data to set flags indicative of the exponent. A circuit produces overflow or underflow exception signals based on the flags and an output from the adder.

REFERENCES:
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4768160 (1988-08-01), Yokoyama
patent: 4779220 (1988-10-01), Nukiyama
patent: 4796217 (1989-01-01), Takahashi et al.

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