Floating point processor architecture which performs square root

Details Floating point processor architecture which performs square root Floating point processor architecture which performs square root

1981-12-28

1984-10-16

Ruggiero, Joseph F.

Boots, shoes, and leggings

364748, 364736, G06F 7552

Patent

active

044778791

ABSTRACT:
There is shown and described a floating point processor having improved architecture and configuration. The floating point processor (FPP) performs addition, subtraction, multiplication, division and square root operations. Usually, the square root operation is not built into the FPP hardware because of the increased complexity of the design, and, therefore, cost of the goods. Rather, the square root operation is usually implemented by firmware or software. The device of this invention performs the floating point square root operation in hardware rather than in software or firmware while adding very little additional hardware to existing circuitry which is required for the basic addition, subtraction, multiplication and division operations. In addition, the operations are performed as rapidly as, or more rapidly than, prior art devices.

REFERENCES:
patent: 3576983 (1971-05-01), Cochran
patent: 3631230 (1971-12-01), Chen
patent: 3906210 (1975-09-01), Mignot
patent: 4126898 (1978-11-01), Spangler et al.
patent: 4336599 (1982-06-01), Wong

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