Floating point processor architecture

Details Floating point processor architecture Floating point processor architecture

1988-01-29

1990-04-10

Clark, David L.

Boots, shoes, and leggings

G06F 738

Patent

active

049166514

ABSTRACT:
A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.

REFERENCES:
patent: 4393468 (1983-07-01), New
patent: 4435765 (1984-03-01), Uchida et al.
patent: 4682302 (1987-07-01), Williams
patent: 4683547 (1987-07-01), DeGroot
patent: 4761753 (1988-08-01), Izumisawa
J. Cates, "Swift 32-Bit Processor and Companion Sequencer Untangle Programming", Electronic Design, Apr. 17, 1986, pp. 137-143.

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