Floating point power conservation

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Details

39575004, G06F 132

Patent

active

057269211

ABSTRACT:
An apparatus comprising floating point circuitry and first logic coupled to at least one flag in a processor control register (e.g. one of the control registers in the Intel Architecture brand processor or a processor compatible therewith) and the floating point circuitry and for coupling to a clock which drives the floating point circuitry. The first logic allows the clock to clock the floating point circuitry when the at least one flag has a first state. The first logic further prevents the clock from clocking the floating point circuitry when the at least one flag has a second state.

REFERENCES:
patent: 4418969 (1983-12-01), Matsuzaki et al.
patent: 5392437 (1995-02-01), Matter et al.
patent: 5420808 (1995-05-01), Alexander et al.
patent: 5586332 (1996-12-01), Jain et al.
patent: 5603037 (1997-02-01), Aybay

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