Floating point pipeline with a leading zeros anticipator...

Details Floating point pipeline with a leading zeros anticipator... Floating point pipeline with a leading zeros anticipator...

1999-06-17

2003-04-01

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06542915

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to a leading zeros anticipator used in floating-point pipelines.
BACKGROUND INFORMATION
Typically, floating point pipelines provide some means for renormalizing floating point data after performing some arithmetic operation, such as an add, multiply, divide, or subtract. Recall that a normalized number is one in which there is exactly one leading ‘1’ prior to the binary point in the mantissa. Since the result of the leading ‘1’ after an arithmetic operation may vary prior to normalization, the position of the leading ‘1’ must be calculated prior to normalization.
For any arithmetic operation which performs an effective add of the operands (in which “effective add” is defined as the addition of two positive or two negative operands, or the subtraction of a negative operand from a positive operand), the position of the leading “1” in the sum is easily calculated within a one binary-digit uncertainty by comparing the magnitudes of the operands' exponents and choosing the position of the leading “1” in the operand with the largest exponent.
For an effective subtract operation, the operands may result in massive cancellation, and a large number of leading zeros may be generated in the resulting sum. The position of the leading “1” can be detected by either a “Leading Zeros Detector” (LZD) circuit, or anticipated by a “Leading Zeros Anticipator” (LZA) circuit.
A “Leading Zeros Detector” is typically implemented as an N-way “OR” gate, one for each bit position in the sum. Each bit is an effective “OR” of all the preceding bits. In this way, a vector is generated which indicates the position of the first leading “1” in the sum. A disadvantage of the LZD is that it introduces additional delay because the sum must be completed before the leading zero may be detected.
A “Leading Zeros Anticipator” avoids some of this additional delay by computing or anticipating the position of the first leading “1” in parallel with the final add which generates the sum. In this way, much of the delay of the LZD can be “hidden”, at the cost of some slight additional hardware.
A disadvantage of the LZA is that not all of the extra delay can be hidden. Typically, the output of the LZA is encoded to provide two functions (typically in the next pipeline stage). The first function, is a “Count Leading Zeros” (CLZ) value which is simply a binary representation of the position of the first leading “1” in the sum. The second function provided by the LZA is that of the normalizer mux (multiplexor) selects, also used in the next pipeline stage. This encoding for either function can be very time-consuming and delays the normalization process.
Many FPU (floating point unit) designs already use the most efficient method of recoding the LZA output into a CLZ value and normalizer mux select signals. Therefore, the only method of speeding up the entire LZA function is apparently to begin computation of the LZA vector earlier than is currently performed.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing need by providing a five-input LZA architecture which can compute the LZA based on five inputs rather than the two inputs used by all LZA implementations prior to this invention. By beginning computation of the LZA with five inputs, the LZA inputs can be moved up to two stages prior to the adder inputs. Usually, these two stages are composed of “Carry-Save Adders” (CSAs), also sometimes known as “Compressors.” By bypassing these two additional CSA stages, computation of the LZA function may begin and end sooner, allowing for significantly faster pipeline and thus processor speeds.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


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