Floating point operation unit in division and square root operat

Details Floating point operation unit in division and square root operat Floating point operation unit in division and square root operat

1989-06-30

1991-03-12

Shaw, Dale M.

Boots, shoes, and leggings

G06F 738

Patent

active

049998013

ABSTRACT:
A floating point operation unit comprises an exponent operation circuit, a sign operation circuit and a mantissa operation circuit. The mantissa operation circuit comprises a fixed point multiplier, a first right shifter, an incrementer, a rounding off controller, a second right shifter, and further, an inversion circuit between the first right shifter and the incrementer. By controlling the inversion circuit and the rounding off controler when one operation of an iterative approximation in a division or a square root operation is executed, the number of cycles in the above operation is reduced, and as a result, the operating speed is increased.

REFERENCES:
patent: 4607343 (1986-08-01), Chevillat et al.
patent: 4707798 (1987-11-01), Nakano
"WTL 1032/1033 Floating Point Division/Square Root/IEEE Arithmetic", WEITEK Preliminary Release Application Note.

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