Floating-point normalizing circuit

Details Floating-point normalizing circuit Floating-point normalizing circuit

1986-12-24

1988-12-27

Malzahn, David H.

Boots, shoes, and leggings

36471504, G06F 738

Patent

active

047945575

ABSTRACT:
A floating-point normalizing circuit is adapted to receive two multi-bit numbers so as to generate a signal indicative of a shift amount for floating-point normalization. The normalizing comprises a plurality of unitary circuits each including a pair of binary inputs, a unitary shift signal output, a carry input, a carry output internally but disconnectably connected to the carry input. These unitary circuits are adapted to receive at their binary inputs different digit position bits of each of the two input numbers, respectively, but each of the unitary circuits receives at its one pair of binary inputs the same digit position bits of the two input numbers. The carry input of each unitary circuit is connected to the carry output of an adjacent more significant digit unitary circuit so that a carry signal is transferred from a more significant digit unitary circuit to a less significant digit unitary circuit. Each of the unitary circuit generates a unitary shift signal when a predetermined logic level is detected in at least one input of the binary inputs and a predetermined carry signal is received at its carry input, and also disconnects the internal connection between the carry input and output, whereby the position of the unitary circuit generating the unitary shift signal is indicative of the amount of required shift for normalization.

REFERENCES:
patent: 4335372 (1982-06-01), Aufderheide et al.
patent: 4553220 (1985-11-01), Swanson
patent: 4586154 (1986-01-01), Berry

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