Floating point multiplier with reduced critical paths using dela

Details Floating point multiplier with reduced critical paths using dela Floating point multiplier with reduced critical paths using dela

1995-07-05

1998-08-04

Mai, Tan V.

Boots, shoes, and leggings

364754, 36474809, G06F 752, G06F 744

Patent

active

057904464

ABSTRACT:
A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53.times.53 double-precision product. Delay matching techniques in the binary tree stage and in the final addition stage reduce cycle time. Improved rounding and sticky-bit generating techniques further reduce area and timing. The overall multiplier has a latency of 3 cycles, a throughput of 1 cycle, and a cycle time of 6.0 ns.

REFERENCES:
patent: 5150319 (1992-09-01), Zyner
patent: 5504915 (1996-04-01), Rarick
patent: 5544084 (1996-08-01), Fukumoto
W.K. Luk and J.E. Vuillemin, "Recursive Implementation of Optimal Time VLSI Integer Multipliers", VLSI 1983, F. Anceau and E.J. Aas, Elsevier Science Publishers, pp. 155-168.
Masato Nagamatsu, Shigeru Tanaka, Junji Mori, Tatsuo Noguchi and Kazuhisa Hatanaka, "A 15 NS 32.times.32-Bit CMOS Multiplier with an Improved Parallel Structure" IEEE 1989 Customer Integrated Circuits Conference, pp. 10.3.1-10.3.4.
Yoshihisa Harata, Yoshio Nakamura, Hiroshi Nagase, Mitsuharu Takigawa, Naofumi Takagi, "A High-Speed Multiplier Using a Redundant Binary Adder Tree", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 1, Feb. 1987, pp. 28-34.
Yoshihisa Harata, Yoshio Nakamura, Hiroshi Nagase, Mitsuharu Takigawa, Naofumi Takagi, "High Speed Multiplier Using a Redundant Binary Adder Tree", pp. 165-170.

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