Floating-point multiplier for de-normalized inputs

Details Floating-point multiplier for de-normalized inputs Floating-point multiplier for de-normalized inputs

2001-01-18

2004-02-24

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06697833

ABSTRACT:

BACKGROUND OF THE INVENTION
This disclosure relates to high speed implementation of floating-point multiplication with floating-point multipliers using the IEEE-754 binary floating-point standard, and in particular, to the handling of de-normalized input operands.
The “IEEE-754 Standard for Binary Floating-point Arithmetic” specifies a floating-point data architecture that is commonly implemented in computer hardware such as floating-point processors having multipliers. The format consists of a sign, a characteristic, and a mantissa. The sign bit is a single bit and is represented by an “S”. The characteristic, represented by a “C”, is 8 bits long for single format and 11 bits long for double format. The mantissa is 24 bits long for single format and 53 bits long for double format. The most significant bit of the mantissa is implied from the value of the characteristic. The lesser significant bits of the mantissa or fraction are represented by “F” in equations (1) and (2) that follow. If the characteristic “C” is not equal to zero, including where it has all bits set to one, then the value of the floating-point number is given by the following equation:
(−1)
S
×(1).
F
×2
(C-Bias)
  (1)
Numbers within this range are called normalized numbers and they have an implied one at the beginning of the mantissa. Numbers outside this range are considered to be special numbers. There are four types of special numbers defined in the IEEE-754 Standard. Three of these special numbers are handled easily by the hardware since their value dictates the resultant value with little or no arithmetic computation. These three special numbers are zero, infinity and not-a-number (“NaN”). The fourth type of special number is a de-normalized number that is indicated by a characteristic equal to zero and a non-zero fraction. The value of the fourth special number is given by the following equation:
(−1)
S
×(0).
F×
2
(1-Bias)
  (2)
In contrast with the normalized format, there is no implied one preceding the fraction in this de-normalized format. In order to determine that the data is de-normalized, the characteristic must be examined. This is important since the computation that is performed by the hardware is typically serially gated by the predetermination of de-normalized input data that will contribute to the cycle time of the hardware, as in the case of multiplication. The handling of de-normalized input data is a particular problem for floating-point processors that do not have any pre-decoded information that an operand is de-normalized, particularly where the assumption is that an input operand is normalized.
There is an additional problem in correcting the product for de-normalized input operands since one operand, the multiplier, is typically Booth scanned and the other, the multiplicand, is typically multiplexed to create partial products to be summed. Post-multiplication correction that adds to the delay of the multiplication process is undesirable. In some floating-point systems, de-normalized input operands cause a trap which allows software to implement them. In other systems the input data is predetermined to be de-normalized, so there is no critical path in performing the correction.
In typical floating-point systems, register and memory (“RX”) format instructions must be implemented at high speed, and there is no time remaining in the cycle prior to execution, which comprises the fetch of the operand from memory, in order to check for de-normalized operands. Accordingly, a solution to handle de-normalized input data is desired that does not adversely impact the performance of the multiplier.
SUMMARY OF THE INVENTION
A method is disclosed for efficiently multiplying de-normalized floating-point numbers without necessarily incurring additional delay over the multiplication of normalized numbers, wherein the de-normalized numbers are initially assumed to be normalized. The method includes providing multiplier and multiplicand floating-point numbers, each defining a fraction and an exponent; encoding the multiplier fraction; multiplexing the multiplier fraction; and multiplying the multiplier fraction by the multiplicand fraction to form a first set of partial products. The method further includes detecting a zero-value multiplier exponent characteristic indicative of de-normalization; computing a last partial product according to the value of the multiplier exponent characteristic; detecting a zero-value multiplicand exponent characteristic indicative of de-normalization; selecting a de-normalized multiplicand correction term according to the detected multiplicand exponent characteristic and the value of the multiplier fraction; and adding each of the first set and the last partial products to the de-normalized multiplicand correction term to form a final product.


REFERENCES:
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patent: 6099158 (2000-08-01), Gorshtein et al.
patent: 6446104 (2002-09-01), Tzeng et al.
IEEE Standard for Binary Floating-Point Arithmetic, The Institute of Electrical and Electronics Engineers, Inc., 1985.

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