Floating-point multiplier circuit for generating the sticky-bit

Details Floating-point multiplier circuit for generating the sticky-bit Floating-point multiplier circuit for generating the sticky-bit

1997-06-25

1999-08-31

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 738

Patent

active

059447737

ABSTRACT:
A circuit for generating the sticky-bit includes a first encoder, a second encoder and an adder circuit. The first and second encoders respectively provide encoded values representing the number of trailing zeros in the first and second operands of the multiplication operation. The adder receives the encoded values from the encoders and a constant. The constant represents the number of bits used in determining the sticky-bit. The adder circuit then adds the encoded values together to generate a sum representing the number of trailing zeros in the resultant. The adder circuit then compares the sum to the constant. If the sum is larger than the constant, then the sticky-bit is given a value of zero and, conversely, if the sum is smaller than the constant, the sticky-bit is given a value of one.

REFERENCES:
patent: H1222 (1993-08-01), Brown et al.
patent: 4928259 (1990-05-01), Galbi et al.
Brent, Richard P. and Kung, H. T., "A Regular Layout for Parallel Adders" IEEE Transactions On Computers vol. C-31:260-264 (1982).
Santoro, Mark R. et al., "Rounding Algorithms for IEEE Multipliers" Proceedings of the 9th Symposium on Computer Arithmetic (1989).
Yu, Robert K. and Zyner, Gregory B., "167 MHz Radix-4 Floating Point Multiplier" Proceedings of the 12th Symposium on Computer Arithmetic (1995).
"IEEE Standard for Binary Floating-Point Arithmetic", ANSI/IEEE Std 754-1985, New York, The Institute of Electrical and Electronic Engineers, Inc., (1985).
UltraSPARC.TM. Programmer Reference Manual, Rev. 1.0, Sun Microsystems, Inc., p. 237 (1995).

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