Floating point multiplier capable of easily performing a failure

Details Floating point multiplier capable of easily performing a failure Floating point multiplier capable of easily performing a failure

1994-03-07

1995-07-04

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

054306680

ABSTRACT:
A floating point multiplier includes an exponential part adder for receiving and adding exponential parts of a multiplied value and a multiplying value and outputting an exponential addition result, a binary multiplier for receiving and multiplying mantissa of the multiplied value and the multiplying value and for outputting the multiplication result, an OR gate inputting for receiving a predetermined number of lower order bits of the multiplication result and outputting a logical sum of the lower order bits as a sticky bit, rounding process and normalization process circuit for receiving a predetermined number of higher order bits of the multiplication result and the sticky signal, performing a rounding process and a normalizing process for the higher order bits of the multiplication result on the basis of the sticky bit, coupling a result of normalization with the addition result of the exponential parts and outputting a final multiplication result, and a selection circuit for receiving the final multiplication result and the lower order bits of the multiplication result of the binary multiplier and selectively outputting.

REFERENCES:
patent: 5150319 (1992-09-01), Zyner
patent: 5150320 (1992-09-01), Nakayama
patent: 5197023 (1993-03-01), Nakayama
patent: 5268854 (1993-12-01), Ikumi
patent: 5303175 (1994-04-01), Suzuki
"IEEE Standard for Binary Floating-Point Arithmetic", American National Standard, pp. 1-18, (1985).

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