Floating point/integer processor with divide and square root fun

Details Floating point/integer processor with divide and square root fun Floating point/integer processor with divide and square root fun

1988-01-29

1989-10-31

Harkcom, Gary V.

Boots, shoes, and leggings

364761, G06F 738

Patent

active

048781908

ABSTRACT:
A processor (10) operable to calculate division and square root functions comprises a multiplier (48) having a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52). The products generated by the multiplier array (116) are fed back to the multiplier (48) to avoid delays associated with the remainder of the multiplier circuitry. The correction generator (122) which performs a subtraction of the product output form the multiplier array (116) from a constant, is disposed between the multiplier array (116) and the converter/rounder (52). Hence, the subtraction necessry to compute the next estimate may be performed in parallel with other multiplications, further reducing the time necessary to perform the calculation. Compare circuitry (120) is operable to compare the final approximation with an operand to quickly determine the direction of rounding.

REFERENCES:
patent: 3631230 (1971-12-01), Chen
patent: 4638449 (1987-01-01), Frey
patent: 4707798 (1987-11-01), Nakamo
patent: 4724529 (1988-02-01), Imkulla et al.
patent: 4761758 (1988-08-01), Deczky et al.

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