Boots – shoes – and leggings
Patent
1992-11-09
1994-05-03
Mai, Tan V.
Boots, shoes, and leggings
364761, G06F 738, G06F 752
Patent
active
053093836
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a floating-point division circuit, and more particularly to a division circuit for performing division of floating-point data defined by the Institute of Electrical and Electronics Engineers (IEEE) standard.
A vector arithmetic unit in a vector processor performs addition, subtraction, multiplication, and division of vector data. Such a vector arithmetic unit is mounted in a large scale semiconductor circuit (LSI) and division of vector data is conventionally performed by a multiplication circuit thereof. Since it is desirable, in terms of increasing the speed and operational precision of a vector processor, that each of the arithmetic operations be performed in a parallel manner by specialized circuits, recently division circuits have been provided separately from multiplication circuit.
However, providing a division circuit separately from a multiplication circuit leads to increased power consumption of LSI due to the addition of a division circuit. This increase necessitates a reduction in power consumption of a division circuit.
BACKGROUND ART
A floating-point division circuit executes an instruction for division by repeating a recursive procedure defined by the following equation. is either 0 or an integer in the range of 1 to n-1, D a divisor, q.sub.j + 1 a (j + 1)th quotient digit counting from a decimal point (q.sub.0 is a sign), n a digit length of a quotient, r a radix, r .times. R (j) a partial dividend before the (j + 1)th quotient digit is determined, R (j + 1) a partial remainder after the (j + 1)th quotient digit is determined, R (0) a dividend (initial value of the partial dividend), R (n) a final remainder.
The quotient Q is expressed by a series of (n + 1) quotient digits q.sub.0 - q.sub.n, as shown in the following equation.
Accordingly, most of the time needed for an execution of a division is spent on a repetition of the above-mentioned recursive procedure. One approach to reduce the repetitions of this recursive procedure, so that division is speedily performed, is known as a non-recovery type division method. In this non-recovery type division method, attention is paid to the fact that a set of quotients used for generating a quotient digit q.sub.j + 1 could be a set of signed quotients not including 0, before selecting the quotient digit from the quotient set. Assuming that r is a radix, the above-mentioned set of signed quotients can be given by:
This non-recovery type division method is characterized in that negative numbers are allowed to represent digits of the result of an operation by not recovering a reversal from positive to negative dividend, the reversal arising when determining each digit of the result of the operation; and that the divisor or a multiple of the divisor is added to or subtracted from the digit, depending on the sign of the dividend; the method is hence called a separation method.
In this method, a quotient is obtained by first placing, in a divisor register, a data for a multiple of the divisor that is k times the divisor (obtained by multiplying the divisor by each quotient of the above-mentioned set of signed quotients), selecting the above-mentioned divisor register on the basis of a prediction signal output from a quotient predicting device, and repeating addition or subtraction of the multiple of the divisor that is k times the divisor.
One variation of this non-recovery type division method, employed when a faster and more accurate division is to be performed, is known as a large-radix non-recovery division method that reduces the number of loops of division by increasing the radix r so that the number of bits that serve as an operation unit is relatively large.
A division circuit of this configuration can speed up an operation of a vector processor by having a division circuit running parallel with an addition circuit, a subtraction circuit, and a multiplication circuit. It should be noted, however, that addition, subtraction, multiplication, and division circuits do not receive an operatio
REFERENCES:
patent: 4760550 (1988-07-01), Katzman et al.
patent: 4996660 (1991-02-01), Beacom et al.
patent: 4999801 (1991-03-01), Katsuno
8084 IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 36, No. 2, Feb. 1988, New York, N.Y., USA, Architectural Strategies for an Application-Specific Synchronous Multiprocessor Environment, F. Catthoor et al., pp. 265-238.
Patent Abstract of Japan, JP3091028, Apr. 16, 1991.
Fujitsu
Mai Tan V.
LandOfFree
Floating-point division circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Floating-point division circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating-point division circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2120310