Floating point divide and square root processor

Details Floating point divide and square root processor Floating point divide and square root processor

2005-01-25

2005-01-25

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S504000

Reexamination Certificate

active

06847985

ABSTRACT:
An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimated partial remainder W[j+1] for the next iteration, j+1, as 2*W[j]−Sj+1*D, where W[j] is the estimated partial remainder for the current iteration calculated during the prior iteration, Sj+1is the quotient bit estimated for the next iteration, and D is the respective divisor bit. The estimated quotient bit for the next iteration is selected based on the calculated partial remainder. In the square-root mode, the first summing device calculates 2W[j]−2S[j]Sj+1, where W[j] is the estimated partial remainder and Sj+1is the estimated result generated during the current iteration, j. A shift register shifts the value of the estimated result, Sj+1, to generate −Sj+12·2−(j+1), which is summed with the result from the first summing device to generate the estimated partial remainder for the square root mode.

REFERENCES:
patent: 5404324 (1995-04-01), Colon-Bonet
patent: 5870323 (1999-02-01), Prabhu et al.
patent: 6108682 (2000-08-01), Matheny

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