Floating point data processor having fast access memory means

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G06F 1306

Patent

active

041797345

ABSTRACT:
A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle. Memory registers comprise a data pad having a plurality of selectable stack registers and means for writing information into said data pad during one clock cycle for retrieval during the next clock cycle.

REFERENCES:
patent: 3411142 (1968-11-01), Lee et al.
patent: 3651476 (1972-03-01), Metz et al.
patent: 3928857 (1975-12-01), Carter et al.
patent: 4087853 (1978-05-01), Kashio

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