Floating point data processor for high speech operation

Details Floating point data processor for high speech operation Floating point data processor for high speech operation

1976-07-02

1978-02-21

Malzahn, David H.

Boots, shoes, and leggings

364200, G06F 738

Patent

active

040757048

ABSTRACT:
A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle.

REFERENCES:
patent: 3697734 (1972-10-01), Booth et al.
patent: 3701976 (1972-10-01), Shively
patent: 3731284 (1973-05-01), Thies
patent: 3771141 (1973-11-01), Culler
patent: 3871578 (1975-03-01), Van De Goor et al.
patent: 3969702 (1976-07-01), Tessera

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