Floating point data adder

Details Floating point data adder Floating point data adder

1984-04-11

1987-02-17

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

046444904

ABSTRACT:
A pipelined adder for adding or subtracting two floating point input data each expressed by a sign data, an exponent data and a mantissa expressed in a sign-magnitude format, in accordance with an external operation mode designation signal to produce a floating point sum or difference data in a sign-magnitude format. In a first stage of the adder, the magnitudes of the exponent data of the input data are compared by a subtractor or a comparator and the magnitudes of the mantissa data of the input data are compared by a subtractor or a comparator. An actual operation mode for the mantissa data of the input data is determined, on the basis of the compare results of the exponent data and the mantissa data and the external operation mode designation signals, so that the operation result data is always expressed in a sign-magnitude format.

REFERENCES:
patent: 3551665 (1970-12-01), Powers et al.
patent: 3697734 (1972-10-01), Booth et al.
patent: 4075704 (1978-02-01), O'Leary
patent: 4229801 (1980-10-01), Whipple
patent: 4562553 (1985-12-01), Mattedi et al.
Covert et al, "Floating-Point Adder Chip Fills Digital-Processing Gap" Electronic Design, vol. 29, No. 24, Nov. 26, 1981, pp. 187-192.

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