Floating point condition code generation

Details Floating point condition code generation Floating point condition code generation

1986-10-14

1987-07-28

Malzahn, David H.

Boots, shoes, and leggings

3401462, G06F 748

Patent

active

046835466

ABSTRACT:
A method and apparatus for generating floating point condition codes by using the data type of a result operand, rather than a magnitude relationship between two operands. The condition codes may then be combined to generate relations useful for identifying conditions for conditional branches or traps.

REFERENCES:
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patent: 3825895 (1974-07-01), Larson et al.
patent: 4429370 (1984-01-01), Blau et al.
Dumstorff et al. "Arithmetic Logical Unit A-Register Addressbility to Improve Microprocessor Compare Capability" IBM Tech. Disclosure Bulletin vol. 15, No. 3, pp. 1059-1060 Aug. 1972.
Chroust, "Simulating Logical Comparisons Using Arithmetic `With Carry` OperOperations" IBM Tech. Disclosure Bulletin vol. 23, No. 4, pp. 1506-1507, Sep. 1980.
Stucka, "Using a Four-Bit Adder as a Comparator" IBM Tech. Disclosure Bulletin, vol. 26, No. 2, pp. 569-571, Jul. 1983.

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