Floating point circuit with configurable number of multiplier cy

Details Floating point circuit with configurable number of multiplier cy Floating point circuit with configurable number of multiplier cy

1988-03-14

1990-02-13

Malzahn, David H.

Boots, shoes, and leggings

364748, G06F 738

Patent

active

049012673

ABSTRACT:
The present invention optimizes the number and ratio of cycles required among the divide/square root unit, multiplier unit and ALU. An intermediate latch with its own clock is provided at the output of the multiplier half-array in the intermediate stage to feed back data for a second pass for double-precision numbers. The multiplier can then be adjusted for either two-cycle latency mode (for optimizing double-precision multiplies) or three-cycle latency mode (for optimizing single-precision multiplies). A separate divide clock is used for the divide/square root unit, and is synchronized with the multiplier cycle clock on input and output. This allows the divide time to be optimized so that it requires fewer clock cycles when a longer multiplier clock cycle time is used.

REFERENCES:
patent: 4075704 (1978-02-01), O'Leary
patent: 4507728 (1985-03-01), Sakamoto et al.
patent: 4612628 (1986-09-01), Beauchamp
patent: 4754421 (1988-06-01), Bosshart
Windsor, II, "IEEE Floating Point Chips Implement DSP Architectures", Computer Design, Jan., 1985, pp. 165-170.

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