Floating-point calculation apparatus

Details Floating-point calculation apparatus Floating-point calculation apparatus

1999-03-24

2003-06-10

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S201000

Reexamination Certificate

active

06578060

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to floating-calculation apparatuses and, more particularly to an apparatus for floating-point addition and subtraction using a digital circuit. More specifically, the present invention relates to a structure of a circuit for addition and subtraction of exponent values in order to align fraction parts for floating-point addition and subtraction.
2. Description of the Background Art
FIG. 16
is a diagram showing a structure of a format for floating-point representation. Referring to
FIG. 16
, a floating-point number has an exponent part storing an exponent value E, a fraction part storing a fraction value (or a mantissa value) F and a sign part storing a sign bit SG representing a sign of the fraction value of the fraction part. The floating-point number is represented by (−1)
SG
·(1.F)2
E+BIAS
. Here, “BIAS” represents a bias value for normalization. The fraction and exponent values are generally represented by the hexadecimal system.
Such floating-point number can accommodate a significant number with a large number of digits, and is widely used for scientific calculation or the like.
For addition or subtraction of such floating-point numbers, digits thereof must be aligned as in the case of a usual addition or subtraction of the decimal numbers. Thus, for floating-point addition or subtraction, a fraction part of a smaller floating-point number is right-shifted (logic right-shifted), so that the exponent values of the floating-point numbers, between which addition or subtraction is performed, can be equalized.
Now, digit alignment of two operands NA and NB will be considered with reference to FIG.
17
(A). Operand NA is represented in the floating-point representation using the hexadecimal system, and has a sign bit, exponent value and fraction value of 0, “43” and “65123A”, respectively. The second operand NB has the sign bit, exponent value and fraction value of “0”, “3F” and “CBA987”, respectively.
The exponent value “43” of first operand NA is greater than the exponent value “3F” of second operand NB. Thus, in order to make the exponent value “3F” of second operand NB equal to the exponent value “43” of first operand NA, the fraction part of second operand NB is shifted in a right direction and, the exponent value of second operand NB is increased every time the fraction part is shifted.
First, with reference to FIG.
17
(B), the fraction value of second operand NB is right-shifted by 1 bit. In the most significant bit position, “0” is inserted. In other words, logic right-shift is performed on the fraction part. As a result of the right-shift by 1 bit, the exponent value of second operand NB is increased by 1 and turns to “40”.
Thereafter, as shown in FIG.
17
(C), the fraction value of the second operand is further light-shifted by 1 bit, so that the exponent value of the second operand is increased by 1. As the exponent value “41” is still smaller than the exponent value “43” of first operand NA, right-shifting is further performed as shown in FIGS.
17
(D) and
17
(E). As shown in FIG.
17
(E), the exponent value “43” of second operand NA is made equal to the exponent value of first operand NA, and thus digit alignment of the fraction values of first and second operands NA and NB is completed. Subsequently, addition or subtraction of first and second operands NA and NB, respectively shown in FIGS.
17
(A) and
17
(E), is executed.
Thus, for addition or subtraction of the floating-point numbers, determination must be made as to which of the fraction values of two operands must be right-shifted. To that end, it is necessary to compare the exponent values of two operands, determine the operand (floating-point number) to be right-shifted, and calculate the difference of the exponent values to determine an amount to be right-shifted.
FIG. 18
is a diagram schematically showing a structure of a right-shift amount determination portion in a conventional floating-point calculation apparatus. The structure shown in
FIG. 18
is described, for example, in Suzuki et al., “Leading-Zero Anticipatory Logic for High-Speed Floating Point Addition”, IEEE Journal of Solid-State Circuits, vol. 31, #8, pp. 1157-1164, August 1996.
In
FIG. 18
, a shift amount calculation portion calculates a shift amount for two floating-point numbers (operands) NA and NB. Floating-point number NA has an exponent value EA and a fraction value FA, whereas floating-point number NB has an exponent value EB and a fraction value FB.
As shown in
FIG. 18
, the shift amount calculation portion includes two 2's complement subtractors
701
and
702
arranged in parallel, and a comparator
703
for comparing exponent values EA and EB. 2's complement subtractor
701
has its inputs IA and IB respectively receiving exponent values EA and EB, and subtracts exponent value EB applied to input IB from exponent value EA applied to input IA. Here, 2's complement subtractor
701
converts exponent value EB applied to input IB to a 2's complement for addition, and outputs the addition result from an output O. On the other hand, 2's complement subtractor
702
subtracts exponent value EA applied to input IB from exponent value EB applied to input IA, and outputs a value indicating the subtraction result from output O.
Comparator
703
asserts a signal output from 0 “1” when exponent value EA applied to an input CA thereof is equal to or greater than exponent value EB applied to an input CB thereof. When exponent value EA applied to input CA is smaller than exponent value EB applied to input CB, the signal from output O is asserted “0” by comparator
703
.
The shift amount calculation portion further includes: a multiplexer
704
having its inputs I
1
and I
0
respectively receiving output values from 2's complement subtractors
701
and
702
for selecting one of the output values in accordance with an output signal from comparator
703
for outputting from output O; a multiplexer
705
having its inputs I
0
and I
1
respectively receiving fraction values FA and FB of floating-point numbers NA and NB for selecting one of the fraction values in accordance with the output signal from comparator
703
and outputting a fraction value FC; and a multiplexer
706
having its inputs I
0
and I
1
respectively receiving fraction values FB and FA for selecting one of the fraction values in accordance with the output signal from comparator
703
and outputting a fraction value FD from output O. Digit-shifting is performed for fraction value FC from multiplexer
705
by a right-shift circuit (not shown), whereas fraction value FD from multiplexer
706
is not right-shifted and applied to an adder (not shown).
Two 2's complement subtractors
701
and
702
are used with the following reasons. When a large exponent value is subtracted from a small exponent value, a negative value is produced so that a shift amount cannot be determined correctly. For the determination of the shift amount, an absolute value of the difference must be calculated. The 2's complement subtractors
701
and
702
are used for absolute value subtraction for calculating the absolute value of the difference. In 2's complement subtractors
701
and
702
, two exponent values EA and EB are applied in reversed arrangements. Thus, one subtractor produces a positive value, and the other produces a negative value. Comparator
703
determines which of the subtractors outputs the negative value. The absolute value of the difference |EA−EB| between exponent values EA and EB determines a right-shift amount of the fraction value. On the other hand, the output signal from comparator
703
also indicates which of the fraction values must be right-shifted, and multiplexers
705
and
706
select the fraction value to be right-shifted and that not to be right-shifted. Now, the operation will briefly be described.
The 2's complement subtractors
701
and
702
respectively produce values (EA−EB) and (EB&mi

Affiliated with

Also associated with

Rating

Floating-point calculation apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating-point calculation apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating-point calculation apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3155066